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author | Marek BehĂșn <marek.behun@nic.cz> | 2018-12-21 20:32:57 +0300 |
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committer | Linus Walleij <linus.walleij@linaro.org> | 2019-01-11 11:53:47 +0300 |
commit | 823868fceae3bac07cf5eccb128d6916e7a5ae9d (patch) | |
tree | 87dfbff40a3856fe54aef986bee5439fe76a3e56 /Documentation/devicetree/bindings | |
parent | f05c07b05d67c578d2f11c04482d983dba7ebc9c (diff) | |
download | linux-823868fceae3bac07cf5eccb128d6916e7a5ae9d.tar.xz |
pinctrl: armada-37xx: Correct mpp definitions
This is a cleanup and fix of the patch by Ken Ma <make@marvell.com>.
Fix the mpp definitions according to newest revision of the
specification:
- northbridge:
fix pmic1 gpio number to 7
fix pmic0 gpio number to 6
- southbridge
split pcie1 group bit mask to BIT(5) and BIT(9)
fix ptp group bit mask to BIT(11) | BIT(12) | BIT(13)
add smi group with bit mask BIT(4)
[gregory: split the pcie group in 2, as at hardware level they can be
configured separately]
Signed-off-by: Marek BehĂșn <marek.behun@nic.cz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r-- | Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt index c7c088d2dd50..f69f82741cae 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt @@ -58,11 +58,11 @@ group pwm3 - functions pwm, gpio group pmic1 - - pin 17 + - pin 7 - functions pmic, gpio group pmic0 - - pin 16 + - pin 6 - functions pmic, gpio group i2c2 @@ -112,17 +112,25 @@ group usb2_drvvbus1 - functions drvbus, gpio group sdio_sb - - pins 60-64 + - pins 60-65 - functions sdio, gpio group rgmii - - pins 42-55 + - pins 42-53 - functions mii, gpio group pcie1 - - pins 39-40 + - pins 39 + - functions pcie, gpio + +group pcie1_clkreq + - pins 40 - functions pcie, gpio +group smi + - pins 54-55 + - functions smi, gpio + group ptp - pins 56-58 - functions ptp, gpio |