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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-04-01 22:57:42 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-04-02 01:09:50 +0300 |
| commit | 2524257bce43610f5ec14feccbacf7a103cae94a (patch) | |
| tree | ef9eff4b37caa4dcd22c4df37ab43113eacef81a /Documentation/devicetree/bindings/riscv | |
| parent | a3dfc532b8731843c12bdc45e804eacc47e51e50 (diff) | |
| download | linux-2524257bce43610f5ec14feccbacf7a103cae94a.tar.xz | |
dt-bindings: Fix phandle-array issues in the idle-states bindings
As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the
phandle-array bindings have been disambiguated. This fixes the new
RISC-V idle-states bindings to comply with the schema.
Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f62f646bc695..d632ac76532e 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -101,6 +101,8 @@ properties: cpu-idle-states: $ref: '/schemas/types.yaml#/definitions/phandle-array' + items: + maxItems: 1 description: | List of phandles to idle state nodes supported by this hart (see ./idle-states.yaml). |