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authorBjorn Helgaas <bhelgaas@google.com>2018-06-07 00:10:27 +0300
committerBjorn Helgaas <bhelgaas@google.com>2018-06-07 00:10:27 +0300
commitf03c7aa4598b78f9f0f6883f1e410f67968f74b9 (patch)
treeb474423af26a7c20838e795fc39bc8795d24cf75 /Documentation/devicetree/bindings/pci
parentbdc4bb13773955d33f8fd23d79afbc95fda8dca4 (diff)
parent854b69efbdd2903991506ac5d5624d2cfb5b4e2f (diff)
downloadlinux-f03c7aa4598b78f9f0f6883f1e410f67968f74b9.tar.xz
Merge branch 'lorenzo/pci/dwc'
- reduce Keystone "link already up" log level (Fabio Estevam) - move private DT functions to drivers/pci/ (Rob Herring) - factor out dwc CONFIG_PCI Kconfig dependencies (Rob Herring) - add DesignWare support to the endpoint test driver (Gustavo Pimentel) - add DesignWare support for endpoint mode (Gustavo Pimentel) - use devm_ioremap_resource() instead of devm_ioremap() in dra7xx and artpec6 (Gustavo Pimentel) - fix Qualcomm bitwise NOT issue (Dan Carpenter) - add Qualcomm runtime PM support (Srinivas Kandagatla) * lorenzo/pci/dwc: PCI: qcom: add runtime pm support to pcie_port PCI: qcom: Fix a bitwise vs logical NOT typo PCI: dwc: dra7xx: Use devm_ioremap_resource() instead of devm_ioremap() PCI: dwc: artpec6: Use devm_ioremap_resource() instead of devm_ioremap() misc: pci_endpoint_test: Add DesignWare EP entry dt-bindings: PCI: designware: Add support for EP in DesignWare driver PCI: dwc: Add support for EP mode dt-bindings: PCI: designware: Example update PCI: Move private DT related functions into private header PCI: dwc: Move CONFIG_PCI depends to menu PCI: dwc: Replace magic number by defines PCI: dwc: Small computation improvement PCI: dwc: Replace lower into upper case characters PCI: dwc: Define maximum number of vectors PCI: imx6: Remove space before tabs PCI: keystone: Do not treat link up message as error # Conflicts: # include/linux/of_pci.h
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
-rw-r--r--Documentation/devicetree/bindings/pci/designware-pcie.txt24
1 files changed, 18 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 1da7ade3183c..c124f9bc11f3 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -1,7 +1,9 @@
* Synopsys DesignWare PCIe interface
Required properties:
-- compatible: should contain "snps,dw-pcie" to identify the core.
+- compatible:
+ "snps,dw-pcie" for RC mode;
+ "snps,dw-pcie-ep" for EP mode;
- reg: Should contain the configuration address space.
- reg-names: Must be "config" for the PCIe configuration space.
(The old way of getting the configuration address space from "ranges"
@@ -41,11 +43,11 @@ EP mode:
Example configuration:
- pcie: pcie@dffff000 {
+ pcie: pcie@dfc00000 {
compatible = "snps,dw-pcie";
- reg = <0xdffff000 0x1000>, /* Controller registers */
- <0xd0000000 0x2000>; /* PCI config space */
- reg-names = "ctrlreg", "config";
+ reg = <0xdfc00000 0x0001000>, /* IP registers */
+ <0xd0000000 0x0002000>; /* Configuration space */
+ reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -54,5 +56,15 @@ Example configuration:
interrupts = <25>, <24>;
#interrupt-cells = <1>;
num-lanes = <1>;
- num-viewport = <3>;
+ };
+or
+ pcie: pcie@dfc00000 {
+ compatible = "snps,dw-pcie-ep";
+ reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
+ <0xdfc01000 0x0001000>, /* IP registers 2 */
+ <0xd0000000 0x2000000>; /* Configuration space */
+ reg-names = "dbi", "dbi2", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
};