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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-07-31 15:21:21 +0300 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2019-08-27 09:07:09 +0300 |
| commit | 0c79cf1f486135929f4370b6d919be0facdc1c8e (patch) | |
| tree | b8ec5962bc102a3d97b25a87f261414072558d08 /Documentation/devicetree/bindings/pci/pci-armada8k.txt | |
| parent | 06a09dc318e4ee91be630a99dc7cd6b92aa44d3d (diff) | |
| download | linux-0c79cf1f486135929f4370b6d919be0facdc1c8e.tar.xz | |
dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
Armada CP110 PCIe controller can have from one to four PHYs for
configuring SERDES lanes (PCIe x1, PCIe x2 or PCIe x4). Describe the
phys and phy-names properties in the bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/pci-armada8k.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/pci-armada8k.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index 9e3fc15e1af8..8324a4ee6f06 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -17,6 +17,14 @@ Required properties: name must be "core" for the first clock and "reg" for the second one +Optional properties: +- phys: phandle(s) to PHY node(s) following the generic PHY bindings. + Either 1, 2 or 4 PHYs might be needed depending on the number of + PCIe lanes. +- phy-names: names of the PHYs corresponding to the number of lanes. + Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for + 2 PHYs. + Example: pcie@f2600000 { |