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| author | Suman Anna <s-anna@ti.com> | 2021-06-23 20:06:30 +0300 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2021-07-15 16:35:48 +0300 |
| commit | 977b3167c2bda24c3cd21e94ca7a4c25a386e812 (patch) | |
| tree | 0a71bd631a5d61137846ffdd8ec7d42202092233 /Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml | |
| parent | fac4e24dcc56b59cfc5f0cbd559a89adc0fc63bf (diff) | |
| download | linux-977b3167c2bda24c3cd21e94ca7a4c25a386e812.tar.xz | |
dt-bindings: irqchip: Update pruss-intc binding for K3 AM64x SoCs
The K3 AM64x SoCs also have a ICSSG IP that is similar to existing K3
AM65x and J721E SoCs. The ICSSG interrupt controller is identical to
that of the INTC on J721E SoCs, and supports 20 host interrupts and
160 input events from various SoC interrupt sources. All the 8 output
host interrupts are routed to multiple entities though. Update the
PRUSS interrupt controller binding with this information, though the
same K3 compatible shall be used for the ICSSG INTC on AM64x SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210623170630.1430-1-s-anna@ti.com
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml index 051beb45d998..65523d9459d8 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml @@ -46,7 +46,7 @@ properties: AM437x family of SoCs, AM57xx family of SoCs 66AK2G family of SoCs - Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs + Use "ti,icssg-intc" for K3 AM65x, J721E and AM64x family of SoCs reg: maxItems: 1 @@ -95,6 +95,8 @@ properties: - AM65x and J721E SoCs have "host_intr5", "host_intr6" and "host_intr7" interrupts connected to MPU, and other ICSSG instances. + - AM64x SoCs have all the 8 host interrupts connected to various + other SoC entities required: - compatible |