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| author | Jay Buddhabhatti <jay.buddhabhatti@xilinx.com> | 2024-01-16 14:58:46 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2024-01-22 16:00:32 +0300 |
| commit | 8e312baaccd296267b41848e362740099157968e (patch) | |
| tree | 930c0e232210f28ceae67056797917269cb8b47b /Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml | |
| parent | 6613476e225e090cc9aad49be7fa504e290dd33d (diff) | |
| download | linux-8e312baaccd296267b41848e362740099157968e.tar.xz | |
dt-bindings: firmware: versal: add versal-net compatible string
Add dt-binding documentation for Versal NET platforms.
Versal Net is a new AMD/Xilinx SoC.
The SoC and its architecture is based on the Versal ACAP device.
The Versal Net device includes more security features in the
platform management controller (PMC) and increases the number of
CPUs in the application processing unit (APU) and the real-time
processing unit (RPU).
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1705406326-2947516-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml')
0 files changed, 0 insertions, 0 deletions