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authorAntoine Ténart <antoine.tenart@free-electrons.com>2014-06-04 20:03:44 +0400
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-06-16 15:17:52 +0400
commita2418f4f049f43a8a5764807436125d753ca716a (patch)
treebec25dc7e3206e52ba1ea458679a0ad0579abc83 /Documentation/devicetree/bindings/arm/cpu-enable-method
parent9ab5fb8ad11ad20e100796ca9b2e43f40de796c3 (diff)
downloadlinux-a2418f4f049f43a8a5764807436125d753ca716a.tar.xz
Documentation: bindings: add the marvell,berlin-smp CPU enable method
Document the CPU enable method used by Marvell Berlin SoCs. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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+========================================================
+Secondary CPU enable-method "marvell,berlin-smp" binding
+========================================================
+
+This document describes the "marvell,berlin-smp" method for enabling secondary
+CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
+be defined in the "cpus" node.
+
+Enable method name: "marvell,berlin-smp"
+Compatible machines: "marvell,berlin2" and "marvell,berlin2q"
+Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
+Related properties: (none)
+
+Note:
+This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
+"marvell,berlin-cpu-ctrl"[1].
+
+Example:
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,berlin-smp";
+
+ cpu@0 {
+ compatible = "marvell,pj4b";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "marvell,pj4b";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <1>;
+ };
+ };
+
+--
+[1] arm/marvell,berlin.txt