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| author | Alok Tiwari <alok.a.tiwari@oracle.com> | 2025-06-22 21:39:16 +0300 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-07-01 02:36:06 +0300 |
| commit | d7b9056c3a6c58d41074b7ba19ab7fd34ce9f63e (patch) | |
| tree | 871568b39303c46fad6b2d0ca97cc428f549999d | |
| parent | 8ad85794be61e046697df8305de34a49791d2ed1 (diff) | |
| download | linux-d7b9056c3a6c58d41074b7ba19ab7fd34ce9f63e.tar.xz | |
cxl/edac: Use correct format specifier for u32 val
The dev_dbg() message in cxl_set_ecs_threshold() used %d for
an unsigned value, which could lead to incorrect logging.
Update the format specifier to %u to match variable type.
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Reviewed-by: Shiju Jose <shiju.jose@huawei.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com?>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20250622183919.4156343-1-alok.a.tiwari@oracle.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
| -rw-r--r-- | drivers/cxl/core/edac.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/cxl/core/edac.c b/drivers/cxl/core/edac.c index 623aaa4439c4..cd3873750e78 100644 --- a/drivers/cxl/core/edac.c +++ b/drivers/cxl/core/edac.c @@ -697,7 +697,7 @@ static int cxl_set_ecs_threshold(struct device *dev, u8 *log_cap, u16 *config, ECS_THRESHOLD_IDX_4096); break; default: - dev_dbg(dev, "Invalid CXL ECS threshold count(%d) to set\n", + dev_dbg(dev, "Invalid CXL ECS threshold count(%u) to set\n", val); dev_dbg(dev, "Supported ECS threshold counts: %u, %u, %u\n", ECS_THRESHOLD_256, ECS_THRESHOLD_1024, |