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| author | Samuel Holland <samuel.holland@sifive.com> | 2025-02-13 04:21:34 +0300 |
|---|---|---|
| committer | Namhyung Kim <namhyung@kernel.org> | 2025-03-11 00:15:37 +0300 |
| commit | d35ad7e881c7a47d9a4834434934df0fd8d54aec (patch) | |
| tree | e21da48ffc169427e901a8c1963b3279a3ab48cd | |
| parent | c1a37db3cf6cb08be5150bd1401b2f584571ddb2 (diff) | |
| download | linux-d35ad7e881c7a47d9a4834434934df0fd8d54aec.tar.xz | |
perf vendor events riscv: Rename U74 to Bullet
This set of PMU event descriptions applies not only to the SiFive U74
core configuration, but also to other SiFive cores that implement the
Bullet microarchitecture (such as U64, P270, and X280). Rename the
directory to be more generic.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Tested-by: Ian Rogers <irogers@google.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20250213220341.3215660-2-samuel.holland@sifive.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
| -rw-r--r-- | tools/perf/pmu-events/arch/riscv/mapfile.csv | 2 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json (renamed from tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json) | 0 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json (renamed from tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json) | 0 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json (renamed from tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json) | 0 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json (renamed from tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json) | 0 |
5 files changed, 1 insertions, 1 deletions
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index 3d3a809a5446..521f416b0006 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -14,7 +14,7 @@ # # #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType -0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core +0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core 0x5b7-0x0-0x0,v1,thead/c900-legacy,core 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json index 7149caec4f80..7149caec4f80 100644 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json index 5eab718c9256..5eab718c9256 100644 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json index be1a46312ac3..be1a46312ac3 100644 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json index 50ffa55418cb..50ffa55418cb 100644 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json |