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authorVille Syrjälä <ville.syrjala@linux.intel.com>2021-05-26 20:35:59 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2021-05-27 18:10:14 +0300
commitd091fc53eb77f8a2a205b41806cfee5674c6a6ae (patch)
tree1b2a01adef75257cfb9478802cf2c91e4c9027b8
parent71c320206a599fa08d5c6b217d930b4c62056c48 (diff)
downloadlinux-d091fc53eb77f8a2a205b41806cfee5674c6a6ae.tar.xz
drm/i915/adl_p: Disable FIFO underrun recovery
The FIFO underrun recovery mechanism has a boatload of cases where it can't be used. The description is also a bit ambiguous as it doesn't specify whether plane downscaling needs to be considered or just pipe downscaling. We may not even have sufficient state tracking to decide this on demand, so for now just disable the whole thing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210526173600.27708-1-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
-rw-r--r--drivers/gpu/drm/i915/display/intel_display.c15
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b4eb48a33caa..55c6a34e11e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2209,6 +2209,21 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
* across pipe
*/
tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
+
+ /*
+ * "The underrun recovery mechanism should be disabled
+ * when the following is enabled for this pipe:
+ * WiDi
+ * Downscaling (this includes YUV420 fullblend)
+ * COG
+ * DSC
+ * PSR2"
+ *
+ * FIXME: enable whenever possible...
+ */
+ if (IS_ALDERLAKE_P(dev_priv))
+ tmp |= UNDERRUN_RECOVERY_DISABLE;
+
intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5fbe5c7a1abe..dd522e45828b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8362,6 +8362,7 @@ enum {
#define _PIPEC_CHICKEN 0x72038
#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
_PIPEB_CHICKEN)
+#define UNDERRUN_RECOVERY_DISABLE REG_BIT(30)
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)