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authormason.huo <mason.huo@starfivetech.com>2022-07-29 06:41:06 +0300
committermason.huo <mason.huo@starfivetech.com>2022-07-29 06:43:13 +0300
commitbfea6096b8cf9d28b468d5321b1fd730fa3cb726 (patch)
treebf8454ae3f08da86440f3fe708abe9638aaf502e
parentb531495da231905b67b730f69be7075b896799df (diff)
downloadlinux-bfea6096b8cf9d28b468d5321b1fd730fa3cb726.tar.xz
riscv: dts: Add Naneng usb2 phy base
Add the Naneng usb2 phy base config, so that driver can access the Naneng usb phy registers. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
-rwxr-xr-xarch/riscv/boot/dts/starfive/jh7110.dtsi3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4398f04b39aa..b39095413cb1 100755
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -375,7 +375,8 @@
usbdrd30: usbdrd{
compatible = "starfive,jh7110-cdns3";
- reg = <0x0 0x10210000 0x0 0x1000>;
+ reg = <0x0 0x10210000 0x0 0x1000>,
+ <0x0 0x10200000 0x0 0x1000>;
clocks = <&clkgen JH7110_USB_125M>,
<&clkgen JH7110_USB0_CLK_APP_125>,
<&clkgen JH7110_USB0_CLK_LPM>,