diff options
| author | pengfuyuan <pengfuyuan@kylinos.cn> | 2022-05-27 06:39:03 +0300 |
|---|---|---|
| committer | Liviu Dudau <liviu.dudau@arm.com> | 2022-07-22 14:54:51 +0300 |
| commit | b62cc8fa824807c00b77a76e78c7417b6bfdf418 (patch) | |
| tree | 1dcafedff65da6026556d8a7bdd09a708659aa40 | |
| parent | ca5f13a21404f5496bcc006d9416c8bef21b227d (diff) | |
| download | linux-b62cc8fa824807c00b77a76e78c7417b6bfdf418.tar.xz | |
drm/arm: Fix spelling typo in comments
Fix spelling typo in comments.
Reported-by: k2ci <kernel-bot@kylinos.cn>
Signed-off-by: pengfuyuan <pengfuyuan@kylinos.cn>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220426121639.39160-1-pengfuyuan@kylinos.cn
| -rw-r--r-- | drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/arm/malidp_regs.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index e672b9cffee3..3276a3e82c62 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -1271,7 +1271,7 @@ int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, return 0; } -/* Since standalong disabled components must be disabled separately and in the +/* Since standalone disabled components must be disabled separately and in the * last, So a complete disable operation may needs to call pipeline_disable * twice (two phase disabling). * Phase 1: disable the common components, flush it. diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index 514c50dcb74d..3bc16db70ddb 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -145,7 +145,7 @@ #define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff #define MALIDP_SE_SET_COEFFTAB_DATA(x) \ ((x) & MALIDP_SE_COEFFTAB_DATA_MASK) -/* Enhance coeffents reigster offset */ +/* Enhance coefficients register offset */ #define MALIDP_SE_IMAGE_ENH 0x3C /* ENH_LIMITS offset 0x0 */ #define MALIDP_SE_ENH_LOW_LEVEL 24 |