diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2021-07-29 20:00:01 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-08-04 07:12:51 +0300 |
| commit | ab49840272cfa595327fa1212a5a44287b9ac986 (patch) | |
| tree | 01bb3872706f6711521fee3522a3c031d6e29762 | |
| parent | eb962fae0078d6f827473e0eb6019db55d2217f1 (diff) | |
| download | linux-ab49840272cfa595327fa1212a5a44287b9ac986.tar.xz | |
drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
DG2 supports compute DSS and has the same maximum number of DSS and EU
as XeHP SDV.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-12-matthew.d.roper@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_sseu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 3a2ff0e00b65..a648818eafa5 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -145,7 +145,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt) * across the entire device. Then calculate out the DSS for each * workload type within that software slice. */ - if (IS_XEHPSDV(gt->i915)) + if (IS_DG2(gt->i915) || IS_XEHPSDV(gt->i915)) intel_sseu_set_info(sseu, 1, 32, 16); else intel_sseu_set_info(sseu, 1, 6, 16); |