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| author | Varadarajan Narayanan <quic_varada@quicinc.com> | 2025-03-17 13:00:26 +0300 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2025-04-26 18:35:26 +0300 |
| commit | a733e711278182840b4c9a0329294daa5cc34048 (patch) | |
| tree | 1d7563bb52475f6bcd049746b5f5be5107903cb6 | |
| parent | d63dbfc6f27de1dd5741107db07b585d344676ee (diff) | |
| download | linux-a733e711278182840b4c9a0329294daa5cc34048.tar.xz | |
dt-bindings: PCI: qcom: Add MHI registers for IPQ9574
The MHI registers are present in IPQ5332, IPQ6018, IPQ8074 and IPQ9574
SoCs. Hence, add the MHI registers to the binding to allow these registers
to be defined in devicetree.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
[mani: commit message rewording]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250317100029.881286-2-quic_varada@quicinc.com
| -rw-r--r-- | Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index e20f142316cc..9cc26d782258 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -175,14 +175,16 @@ allOf: properties: reg: minItems: 5 - maxItems: 5 + maxItems: 6 reg-names: + minItems: 5 items: - const: dbi # DesignWare PCIe registers - const: elbi # External local bus interface registers - const: atu # ATU address space - const: parf # Qualcomm specific registers - const: config # PCIe configuration space + - const: mhi # MHI registers - if: properties: |