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authorAlexander Stein <alexander.stein@ew.tq-group.com>2023-05-17 13:11:07 +0300
committerShawn Guo <shawnguo@kernel.org>2023-05-27 14:01:10 +0300
commita101ba8587fae1dfd7b1bfb13397000a381b0774 (patch)
tree9b5d60c2296cd552b7816a554aac5fd58c01dee5
parent171342e6af06e66a099103f95ede9333aeec28c0 (diff)
downloadlinux-a101ba8587fae1dfd7b1bfb13397000a381b0774.tar.xz
ARM: dts: imx6qdl: Add HDMI to TQMa6x/MBa6
This adds support for a COTS monitor connected to X17. 4k monitors can be used, but are limited to 1080p. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm/boot/dts/imx6qdl-mba6.dtsi41
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi
index c911688e9832..34d5cf7cee0b 100644
--- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi
@@ -192,6 +192,13 @@
};
};
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
&i2c1 {
tlv320aic32x4: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
@@ -205,6 +212,17 @@
};
};
+/* DDC */
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_recovery>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
@@ -411,6 +429,15 @@
>;
};
+ pinctrl_hdmi: hdmigrp {
+ /* NOTE: DDC is done via I2C2, so DON'T
+ * configure DDC pins for HDMI!
+ */
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
+ >;
+ };
+
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
@@ -447,6 +474,20 @@
>;
};
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
+ >;
+ };
+
+ pinctrl_i2c2_recovery: i2c2recoverygrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b899
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b899
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
/* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/