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| author | attreyee-muk <tintinm2017@gmail.com> | 2023-12-23 21:47:20 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-12-29 02:37:36 +0300 |
| commit | 9ca65c373f4451fdf2f82ebc30b17185253aec8f (patch) | |
| tree | 49fd494727651e8e9573c0a48b3162391e134540 | |
| parent | 0942155a48e4cfc2c83e514c86a3de8f78f6af02 (diff) | |
| download | linux-9ca65c373f4451fdf2f82ebc30b17185253aec8f.tar.xz | |
docs: PCI: Fix typos
Fix typos in PCI docs.
Link: https://lore.kernel.org/r/20231223184720.25645-1-tintinm2017@gmail.com
Link: https://lore.kernel.org/r/20231223184412.25598-1-tintinm2017@gmail.com
Signed-off-by: Attreyee Mukherjee <tintinm2017@gmail.com>
[bhelgaas: squashed, commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org> # for "busses" only
| -rw-r--r-- | Documentation/PCI/boot-interrupts.rst | 2 | ||||
| -rw-r--r-- | Documentation/PCI/msi-howto.rst | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/PCI/boot-interrupts.rst b/Documentation/PCI/boot-interrupts.rst index 2ec70121bfca..931077bb0953 100644 --- a/Documentation/PCI/boot-interrupts.rst +++ b/Documentation/PCI/boot-interrupts.rst @@ -61,7 +61,7 @@ Conditions ========== The use of threaded interrupts is the most likely condition to trigger -this problem today. Threaded interrupts may not be reenabled after the IRQ +this problem today. Threaded interrupts may not be re-enabled after the IRQ handler wakes. These "one shot" conditions mean that the threaded interrupt needs to keep the interrupt line masked until the threaded handler has run. Especially when dealing with high data rate interrupts, the thread needs to diff --git a/Documentation/PCI/msi-howto.rst b/Documentation/PCI/msi-howto.rst index c9400f02333b..783d30b7bb42 100644 --- a/Documentation/PCI/msi-howto.rst +++ b/Documentation/PCI/msi-howto.rst @@ -236,7 +236,7 @@ including a full 'lspci -v' so we can add the quirks to the kernel. Disabling MSIs below a bridge ----------------------------- -Some PCI bridges are not able to route MSIs between busses properly. +Some PCI bridges are not able to route MSIs between buses properly. In this case, MSIs must be disabled on all devices behind the bridge. Some bridges allow you to enable MSIs by changing some bits in their |