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| author | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-05-08 09:55:19 +0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-05-20 13:32:20 +0300 |
| commit | 9b7632e8fe7f7e0d75a61dccf2917e55022ecb66 (patch) | |
| tree | 29dc1e65d1146fe938e68c8eaaca5872a0a83731 | |
| parent | f770e91a7b64043dd730b59b5e62d82e71faec63 (diff) | |
| download | linux-9b7632e8fe7f7e0d75a61dccf2917e55022ecb66.tar.xz | |
media: atomisp: fix clock rate frequency setting
changeset d5426f4c2eba ("media: staging: atomisp: use clock framework for camera clocks")
removed a platform-specific code to set the clock rate, in favor of
using the Kernel clock framework.
However, instead of passing the frequency for clk_set_rate(),
it is passing either 0 or 1.
Looking at the original patchset, it seems that there are two
possible configurations for the ISP:
0 - it will use a 25 MHz XTAL to provide the clock;
1 - it will use a PLL with is set to 19.2 MHz
(only for the CHT version?)
Eventually, different XTALs and/or PLL frequencies might
be possible some day, so, re-implent the logic for it to be
more generic.
Fixes: d5426f4c2eba ("media: staging: atomisp: use clock framework for camera clocks")
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
| -rw-r--r-- | drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c b/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c index 783ea48b26fb..bdb4fdebacf5 100644 --- a/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c +++ b/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c @@ -17,7 +17,15 @@ #define MAX_SUBDEVS 8 -#define VLV2_CLK_PLL_19P2MHZ 1 /* XTAL on CHT */ + +enum clock_rate { + VLV2_CLK_XTAL_25_0MHz = 0, + VLV2_CLK_PLL_19P2MHZ = 1 +}; + +#define CLK_RATE_19_2MHZ 19200000 +#define CLK_RATE_25_0MHZ 25000000 + #define ELDO1_SEL_REG 0x19 #define ELDO1_1P8V 0x16 #define ELDO1_CTRL_SHIFT 0x00 @@ -28,7 +36,7 @@ struct gmin_subdev { struct v4l2_subdev *subdev; int clock_num; - int clock_src; + enum clock_rate clock_src; bool clock_on; struct clk *pmc_clk; struct gpio_desc *gpio0; @@ -570,7 +578,7 @@ static int gmin_flisclk_ctrl(struct v4l2_subdev *subdev, int on) return 0; if (on) { - ret = clk_set_rate(gs->pmc_clk, gs->clock_src); + ret = clk_set_rate(gs->pmc_clk, gs->clock_src ? CLK_RATE_19_2MHZ : CLK_RATE_25_0MHZ); if (ret) dev_err(&client->dev, "unable to set PMC rate %d\n", |