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authorShaohua Li <shaohua.li@intel.com>2006-05-26 06:58:27 +0400
committerGreg Kroah-Hartman <gregkh@suse.de>2006-06-21 23:00:00 +0400
commit99dc804d9bcc2c53f4c20c291bf4e185312a1a0c (patch)
tree4798f39176d0f8fe06de446d74cf94ba48423aa9
parent020d502488bebdbc1b2c2828d996f04e563f082a (diff)
downloadlinux-99dc804d9bcc2c53f4c20c291bf4e185312a1a0c.tar.xz
[PATCH] PCI: disable msi mode in pci_disable_device
Brice said the pci_save_msi_state breaks his driver in his special usage (not in suspend/resume), as pci_save_msi_state will disable msi mode. In his usage, pci_save_state will be called at runtime, and later (after the device operates for some time and has an error) pci_restore_state will be called. In another hand, suspend/resume needs disable msi mode, as device should stop working completely. This patch try to workaround this issue. Drivers are expected call pci_disable_device in suspend time after pci_save_state. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/pci/msi.c6
-rw-r--r--drivers/pci/pci.c9
-rw-r--r--include/linux/pci.h2
3 files changed, 14 insertions, 3 deletions
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 9c69b6966e79..3ec558dc6523 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -453,9 +453,11 @@ static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
/* Set enabled bits to single MSI & enable MSI_enable bit */
msi_enable(control, 1);
pci_write_config_word(dev, msi_control_reg(pos), control);
+ dev->msi_enabled = 1;
} else {
msix_enable(control);
pci_write_config_word(dev, msi_control_reg(pos), control);
+ dev->msix_enabled = 1;
}
if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
/* PCI Express Endpoint device detected */
@@ -472,9 +474,11 @@ void disable_msi_mode(struct pci_dev *dev, int pos, int type)
/* Set enabled bits to single MSI & enable MSI_enable bit */
msi_disable(control);
pci_write_config_word(dev, msi_control_reg(pos), control);
+ dev->msi_enabled = 0;
} else {
msix_disable(control);
pci_write_config_word(dev, msi_control_reg(pos), control);
+ dev->msix_enabled = 0;
}
if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
/* PCI Express Endpoint device detected */
@@ -549,7 +553,6 @@ int pci_save_msi_state(struct pci_dev *dev)
pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
if (control & PCI_MSI_FLAGS_MASKBIT)
pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
- disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
save_state->cap_nr = PCI_CAP_ID_MSI;
pci_add_saved_cap(dev, save_state);
return 0;
@@ -639,7 +642,6 @@ int pci_save_msix_state(struct pci_dev *dev)
}
dev->irq = temp;
- disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
save_state->cap_nr = PCI_CAP_ID_MSIX;
pci_add_saved_cap(dev, save_state);
return 0;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index aa480370ef10..d408a3c30426 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -551,7 +551,14 @@ void
pci_disable_device(struct pci_dev *dev)
{
u16 pci_command;
-
+
+ if (dev->msi_enabled)
+ disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
+ PCI_CAP_ID_MSI);
+ if (dev->msix_enabled)
+ disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
+ PCI_CAP_ID_MSIX);
+
pci_read_config_word(dev, PCI_COMMAND, &pci_command);
if (pci_command & PCI_COMMAND_MASTER) {
pci_command &= ~PCI_COMMAND_MASTER;
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 91c37750cd34..62a8c22f5f60 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -163,6 +163,8 @@ struct pci_dev {
unsigned int no_msi:1; /* device may not use msi */
unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
unsigned int broken_parity_status:1; /* Device generates false positive parity */
+ unsigned int msi_enabled:1;
+ unsigned int msix_enabled:1;
u32 saved_config_space[16]; /* config space saved at suspend time */
struct hlist_head saved_cap_space;