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| author | Thierry Reding <treding@nvidia.com> | 2017-12-13 14:43:06 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 14:43:06 +0300 |
| commit | 753863d7f8b739c10c87b8f8c356c7918d37fdcd (patch) | |
| tree | 5ab1276160226e5cae7291f12c822fcb9bec656a | |
| parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
| parent | f580fd3f9d78cf0425ab98950796c578d8a82167 (diff) | |
| download | linux-753863d7f8b739c10c87b8f8c356c7918d37fdcd.tar.xz | |
Merge branch 'for-4.16/dt-bindings' into for-4.16/soc
| -rw-r--r-- | Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt new file mode 100644 index 000000000000..892ba4384abc --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt @@ -0,0 +1,12 @@ +NVIDIA Tegra186 MISC register block + +The MISC register block found on Tegra186 SoCs contains registers that can be +used to identify a given chip and various strapping options. + +Required properties: +- compatible: Must be: + - Tegra186: "nvidia,tegra186-misc" +- reg: Should contain 2 entries: The first entry gives the physical address + and length of the register region which contains revision and debug + features. The second entry specifies the physical address and length + of the register region indicating the strapping options. |