diff options
| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2024-05-07 09:22:44 +0300 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2024-05-10 10:42:53 +0300 |
| commit | 6a3691ca4799997b90da50883c170edb67bd6c49 (patch) | |
| tree | a9ca8b3be896856524f2ea3675d7b3fb1e96610e | |
| parent | 6907d4fa5ecac7b08fb5ee5536e48b0a3895be31 (diff) | |
| download | linux-6a3691ca4799997b90da50883c170edb67bd6c49.tar.xz | |
drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on HDMI
Disable HDCP Line Rekeying when HDCP ver > 1.4 and when we are
on HDMI TMDS operation for DISPLAY_VER >= 14.
--v2
-Wa to be mentioned in comments not in commit message [Jani]
-Remove blankline [Jani]
--v3
-No need to write what is being done in comments when code
is self explanatory [Jani]
--v4
-Add comment regarding need of this WA when in TMDS mode
[Chaitanya]
-Write in chicken register for MTL [CHaitanya]
--v5
-Fix comment [Chaitanya]
-Use correct set and clear value in intel_de_rmw [Chaitanya]
--v6
-No need to define C, D chicken bits it gets calculated [Animesh]
Bspec: 49273
Bspec: 69964
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240507062243.1076047-2-suraj.kandpal@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_hdcp.c | 23 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
2 files changed, 25 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index d5ed4c7dfbc0..02cbbbfd8e25 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -30,6 +30,27 @@ #define KEY_LOAD_TRIES 5 #define HDCP2_LC_RETRY_CNT 3 +/* WA: 16022217614 */ +static void +intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, + struct intel_hdcp *hdcp) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + + /* Here we assume HDMI is in TMDS mode of operation */ + if (encoder->type != INTEL_OUTPUT_HDMI) + return; + + if (DISPLAY_VER(dev_priv) >= 14) { + if (IS_METEORLAKE(dev_priv)) + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), + 0, HDCP_LINE_REKEY_DISABLE); + else + intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder), + 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); + } +} + static int intel_conn_to_vcpi(struct intel_atomic_state *state, struct intel_connector *connector) { @@ -2005,6 +2026,8 @@ static int _intel_hdcp2_enable(struct intel_atomic_state *state, connector->base.base.id, connector->base.name, hdcp->content_type); + intel_hdcp_disable_hdcp_line_rekeying(connector->encoder, hdcp); + ret = hdcp2_authenticate_and_encrypt(state, connector); if (ret) { drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5670eee4a498..adea3882832d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3520,6 +3520,7 @@ #define DP_FEC_BS_JITTER_WA REG_BIT(15) #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) +#define HDCP_LINE_REKEY_DISABLE REG_BIT(0) #define DISP_ARB_CTL _MMIO(0x45000) #define DISP_FBC_MEMORY_WAKE REG_BIT(31) @@ -4521,6 +4522,7 @@ enum skl_power_gate { #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) +#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) |