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| author | Bjorn Helgaas <bhelgaas@google.com> | 2021-11-05 19:28:42 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2021-11-05 19:28:42 +0300 |
| commit | 5e19196c142f040a7d99bcc1540e2052c68231e8 (patch) | |
| tree | 1888883b3d1171a426b68e49a624d5d8890e55c7 | |
| parent | 8d55770b68538d1ea96bd21061851ac093251598 (diff) | |
| parent | e1b0d0bb2032d18c7718168e670d8d3f31e552d7 (diff) | |
| download | linux-5e19196c142f040a7d99bcc1540e2052c68231e8.tar.xz | |
Merge branch 'pci/aspm'
- Re-enable LTR in Downstream Ports after it has been disabled by reset or
hotplug to allow use of ASPM L1.2 again and prevent Unsupported Request
errors when Endpoint sends LTR messages (Mingchuang Qiao)
* pci/aspm:
PCI: Re-enable Downstream Port LTR after reset or hotplug
| -rw-r--r-- | drivers/pci/pci.c | 25 | ||||
| -rw-r--r-- | drivers/pci/pci.h | 1 | ||||
| -rw-r--r-- | drivers/pci/probe.c | 18 |
3 files changed, 41 insertions, 3 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ce2ab62b64cf..17e4341df0ff 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1477,6 +1477,24 @@ static int pci_save_pcie_state(struct pci_dev *dev) return 0; } +void pci_bridge_reconfigure_ltr(struct pci_dev *dev) +{ +#ifdef CONFIG_PCIEASPM + struct pci_dev *bridge; + u32 ctl; + + bridge = pci_upstream_bridge(dev); + if (bridge && bridge->ltr_path) { + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl); + if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { + pci_dbg(bridge, "re-enabling LTR\n"); + pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); + } + } +#endif +} + static void pci_restore_pcie_state(struct pci_dev *dev) { int i = 0; @@ -1487,6 +1505,13 @@ static void pci_restore_pcie_state(struct pci_dev *dev) if (!save_state) return; + /* + * Downstream ports reset the LTR enable bit when link goes down. + * Check and re-configure the bit here before restoring device. + * PCIe r5.0, sec 7.5.3.16. + */ + pci_bridge_reconfigure_ltr(dev); + cap = (u16 *)&save_state->cap.data[0]; pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 1cce56c2aea0..bc7f3a10ff60 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -125,6 +125,7 @@ void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); +void pci_bridge_reconfigure_ltr(struct pci_dev *dev); static inline void pci_wakeup_event(struct pci_dev *dev) { diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index d9fc02a71baa..258350f80f6c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2168,9 +2168,21 @@ static void pci_configure_ltr(struct pci_dev *dev) * Complex and all intermediate Switches indicate support for LTR. * PCIe r4.0, sec 6.18. */ - if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || - ((bridge = pci_upstream_bridge(dev)) && - bridge->ltr_path)) { + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); + dev->ltr_path = 1; + return; + } + + /* + * If we're configuring a hot-added device, LTR was likely + * disabled in the upstream bridge, so re-enable it before enabling + * it in the new device. + */ + bridge = pci_upstream_bridge(dev); + if (bridge && bridge->ltr_path) { + pci_bridge_reconfigure_ltr(dev); pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); dev->ltr_path = 1; |