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authorHuang, Xiong <xiong@qca.qualcomm.com>2012-04-19 02:01:27 +0400
committerDavid S. Miller <davem@davemloft.net>2012-04-20 04:14:20 +0400
commit5cbdcc2f49b4a8372052952799d2cb1de387443b (patch)
tree7a6ad570c04d880a26febdc1ad613e8a3a9a90de
parent7f5544d6693ab2593b4f13521a577387f3be6b2f (diff)
downloadlinux-5cbdcc2f49b4a8372052952799d2cb1de387443b.tar.xz
atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patch
bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend clear it after resume to enable pclk(PCIE clock) switch to low frequency(25M) in some circumstances to save power. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/atheros/atl1c/atl1c_main.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 796cc758c967..9783afc8cb38 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -80,7 +80,12 @@ static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
static void atl1c_pcie_patch(struct atl1c_hw *hw)
{
- u32 data;
+ u32 mst_data, data;
+
+ /* pclk sel could switch to 25M */
+ AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
+ mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
data |= PCIE_PHYMISC_FORCE_RCV_DET;