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| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-10-07 13:17:04 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-10-08 11:33:27 +0300 |
| commit | 46dd40aa376c8158b6aa17510079caf5c3af6237 (patch) | |
| tree | 5f4cb3746c7537b3f1475eaaeada9a9e77244cce | |
| parent | 43fab0856eafb32d5cdb809d8225197755826128 (diff) | |
| download | linux-46dd40aa376c8158b6aa17510079caf5c3af6237.tar.xz | |
MIPS: SGI-IP28: disable use of ll/sc in kernel
SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock
up, if ll/sc sequences are issued in certain order. Since those systems
are all non-SMP, we can disable ll/sc usage in kernel.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| -rw-r--r-- | arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h index ba8b4e30b3e2..613bbc10c1f2 100644 --- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h @@ -25,7 +25,7 @@ #define cpu_has_mcheck 0 #define cpu_has_ejtag 0 -#define cpu_has_llsc 1 +#define cpu_has_llsc 0 #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 /* see probe_pcache() */ #define cpu_has_ic_fills_f_dc 0 |