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author | Pawel Moll <pawel.moll@arm.com> | 2015-08-06 18:05:13 +0300 |
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committer | Michael Turquette <mturquette@baylibre.com> | 2015-08-25 02:48:58 +0300 |
commit | 32ecaf89bdfd842c9669b3f38ff82907e3cd60d0 (patch) | |
tree | bb4506c4ab1ecb59b8940f415a29469db3b99def | |
parent | a53ad8ef3dccb0c5482c60a3f6b8c0cbd498efe5 (diff) | |
download | linux-32ecaf89bdfd842c9669b3f38ff82907e3cd60d0.tar.xz |
clk: versatile: Add SP810 device tree bindings document
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r-- | Documentation/devicetree/bindings/arm/sp810.txt | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/sp810.txt b/Documentation/devicetree/bindings/arm/sp810.txt new file mode 100644 index 000000000000..440ee0892a4d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sp810.txt @@ -0,0 +1,35 @@ +SP810 System Controller +----------------------- + +Required properties: + +- compatible: standard compatible string for a Primecell peripheral, + see Documentation/devicetree/bindings/arm/primecell.txt + for more details + should be: "arm,sp810", "arm,primecell" + +- reg: standard registers property, physical address and size + of the control registers + +- clock-names: from the common clock bindings, for more details see + Documentation/devicetree/bindings/clock/clock-bindings.txt; + should be: "refclk", "timclk", "apb_pclk" + +- clocks: from the common clock bindings, phandle and clock + specifier pairs for the entries of clock-names property + +- #clock-cells: from the common clock bindings; + should be: <1> + +- clock-output-names: from the common clock bindings; + should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3" + +Example: + sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; |