DRM: fixed drm register before i2c controller

DRM: fixed hdmi color problem

Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>

10 files changed, 191 insertions, 211 deletions

diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index 7e8b4cec303e..5fd2bb04ece6 100755
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -448,6 +448,14 @@
 	};
 #endif
 
+#ifdef AC108_ENABLED
+	ac108_a: ac108@3b {
+		compatible = "x-power,ac108_0";
+		reg = <0x3b>;
+		#sound-dai-cells = <0>;
+		data-protocol = <0>;
+	};
+#endif
 	#if 0
 	/* TODO: Used for EVB board, should comment here for starlight board, remove it later*/
 	ov5640: ov5640@3c {
@@ -667,7 +675,7 @@
 				remote-endpoint = <&dsi_out_port>;
 				encoder-type = <6>;	//2-TMDS, 3-LVDS, 6-DSI, 8-DPI
 				reg = <1>;
-				status = "failed";
+				status = "okay";
 			};
 		};
 
@@ -684,3 +692,17 @@
 		};
 	};
 };
+
+&mipi_dphy {
+	status = "okay";
+};
+
+&mipi_dsi {
+	status = "okay";
+
+	port {
+		dsi_out_port: endpoint {
+			remote-endpoint = <&panel_dsi_port>;
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 2e4a7c32ebfd..90ba63dc1660 100755
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -654,10 +654,6 @@
 			status = "disabled";
 		};
 
-		connector0: display-connector {
-			compatible = "starfive,connector-tda998x";
-		};
-
 		encoder: display-encoder {
 			compatible = "starfive,display-encoder";
 			status = "disabled";
@@ -705,7 +701,7 @@
 			clocks = <&uartclk>, <&apb2clk>;
 			clock-names = "baudclk", "apb_pclk";
 			#phy-cells = <0>;
-			status = "okay";
+			status = "disabled";
 		};
 
 		mipi_dsi: mipi@12100000 {
@@ -716,13 +712,7 @@
 			clock-names = "dsi_p_clk", "dsi_sys_clk";
 			phys = <&mipi_dphy>;
 			phy-names = "dphy";
-			status = "okay";
-
-			port {
-				dsi_out_port: endpoint {
-					remote-endpoint = <&panel_dsi_port>;
-				};
-			};
+			status = "disabled";
 		};
 
 		wm8960_mclk: wm8960_mclk {
@@ -730,7 +720,7 @@
 			#clock-cells = <0>;
 			clock-frequency = <24576000>;
 		};
-#if 0
+
 		i2sadc0: i2sadc0@10400000 {
 			compatible = "snps,designware-i2sadc0";
 			reg = <0x0 0x10400000 0x0 0x1000>;
diff --git a/drivers/gpu/drm/starfive/Kconfig b/drivers/gpu/drm/starfive/Kconfig
index 654da53d57c8..3003874cee5b 100755
--- a/drivers/gpu/drm/starfive/Kconfig
+++ b/drivers/gpu/drm/starfive/Kconfig
@@ -2,7 +2,6 @@
 
 config DRM_STARFIVE
 	tristate "DRM Support for StarFive SoCs"
-	default m
 	depends on DRM
 	select DRM_GEM_CMA_HELPER
 	select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/starfive/starfive_drm_crtc.c b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
index c94de56752ca..da3d35641832 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
@@ -37,12 +37,11 @@ static const struct resource_name mem_res_name[] = {
 	{"sys"}
 };
 
-static inline struct drm_encoder *
+struct drm_encoder *
 starfive_head_atom_get_encoder(struct starfive_crtc *sf_crtc)
 {
 	struct drm_encoder *encoder = NULL;
 
-	/* We only ever have a single encoder */
 	drm_for_each_encoder_mask(encoder, sf_crtc->crtc.dev,
 				  sf_crtc->crtc.state->encoder_mask)
 		break;
diff --git a/drivers/gpu/drm/starfive/starfive_drm_crtc.h b/drivers/gpu/drm/starfive/starfive_drm_crtc.h
index 07d79e2b7662..ab81cae24e48 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.h
+++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.h
@@ -82,6 +82,8 @@ struct starfive_crtc {
 };
 #define to_starfive_crtc(x) container_of(x, struct starfive_crtc, crtc)
 
+extern struct drm_encoder *
+starfive_head_atom_get_encoder(struct starfive_crtc *sf_crtc);
 void starfive_crtc_hw_config_simple(struct starfive_crtc *starfive_crtc);
 
 #endif /* _STARFIVE_DRM_CRTC_H */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_drv.c b/drivers/gpu/drm/starfive/starfive_drm_drv.c
index 8690bec69670..4b9f439cfc0d 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_drv.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_drv.c
@@ -171,7 +171,9 @@ static int starfive_drm_bind(struct device *dev)
 	if (ret)
 		goto err_drm_dev_register;
 
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
 	drm_fbdev_generic_setup(drm_dev, 16);
+#endif
 
 	return 0;
 
diff --git a/drivers/gpu/drm/starfive/starfive_drm_encoder.c b/drivers/gpu/drm/starfive/starfive_drm_encoder.c
index 7d3e1317be85..02aa859ecf0c 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_encoder.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_encoder.c
@@ -83,6 +83,8 @@ static int starfive_encoder_bind(struct device *dev, struct device *master, void
 	struct drm_bridge *tmp_bridge;
 	struct starfive_encoder_data *encoder_data = NULL;
 	u32 num_ports = 0;
+	u32 num_bridge = 0;
+	static u32 num_probe = 0;
 
 	num_ports = starfive_encoder_of_parse_ports(dev, &encoder_data);
 
@@ -112,17 +114,37 @@ static int starfive_encoder_bind(struct device *dev, struct device *master, void
 			dev_info(dev, "found panel on endpoint@%d\n",
 				encoder_data[i].endpoint_reg);
 
-		if (!tmp_bridge)
-			dev_err(dev, "can not found bridge on endpoint@%d\n",
-				encoder_data[i].endpoint_reg);
-		else {
-			ret = drm_bridge_attach(&encoderp[i].encoder,
-				tmp_bridge, NULL, 0);
-			if (ret)
-				goto err_bridge;
+		if (!tmp_bridge) {
+			if (encoder_data[i].endpoint_reg == 0) {
+				dev_err(dev, "wait endpoint@%d init\n",
+						encoder_data[i].endpoint_reg);
+				return -EPROBE_DEFER;
+			} else if (encoder_data[i].endpoint_reg == 1) {
+				dev_err(dev, "wait endpoint@%d init\n",
+						encoder_data[i].endpoint_reg);
+
+				num_probe++;
+				if (num_probe > 2) {
+					dev_err(dev, "dont exist endpoint@%d\n",
+							encoder_data[i].endpoint_reg);
+					return -EINVAL;
+				}
+
+				return -EPROBE_DEFER;
+			}
 		}
+
+		ret = drm_bridge_attach(&encoderp[i].encoder,
+			tmp_bridge, NULL, 0);
+		if (ret)
+			goto err_bridge;
+
+		num_bridge++;
 	}
 
+	if (num_bridge < num_ports)
+		return -EINVAL;
+
 	return 0;
 
 err_bridge:
diff --git a/drivers/gpu/drm/starfive/starfive_drm_lcdc.c b/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
index 627e20af16d3..faf760638b40 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
@@ -74,27 +74,30 @@ static void starfive_lcdc_rstwrite32(struct starfive_crtc *sf_crtc, u32 reg, u32
 	iowrite32(val, sf_crtc->base_rst + reg);
 }
 
-void lcdc_mode_cfg(struct starfive_crtc *sf_crtc, uint32_t workMode, int dotEdge, int syncEdge, int r2yBypass,
-					int srcSel, int intSrc, int intFreq)
+static void lcdc_mode_cfg(struct starfive_crtc *sf_crtc, uint32_t workMode, int dotEdge,
+			int syncEdge, int r2yBypass, int srcSel, int intSrc, int intFreq)
 {
 	u32 lcdcEn = 0x1;
-	u32 cfg = lcdcEn | workMode << LCDC_WORK_MODE
-				| dotEdge << LCDC_DOTCLK_P
-				| syncEdge << LCDC_HSYNC_P
-				| syncEdge << LCDC_VSYNC_P
-				| 0x0 << LCDC_DITHER_EN
-				| r2yBypass << LCDC_R2Y_BPS
-				| srcSel << LCDC_TV_LCD_PATHSEL
-				| intSrc << LCDC_INT_SEL
-				| intFreq << LCDC_INT_FREQ;
+	u32 cfg = lcdcEn |
+		workMode << LCDC_WORK_MODE |
+		dotEdge << LCDC_DOTCLK_P |
+		syncEdge << LCDC_HSYNC_P |
+		syncEdge << LCDC_VSYNC_P |
+		0x0 << LCDC_DITHER_EN |
+		r2yBypass << LCDC_R2Y_BPS |
+		srcSel << LCDC_TV_LCD_PATHSEL |
+		intSrc << LCDC_INT_SEL |
+		intFreq << LCDC_INT_FREQ;
 
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_GCTRL, cfg);
 	LCDC_PRT("LCDC WorkMode: 0x%x, LCDC Path: %d\n", workMode, srcSel);
 }
 
-void lcdc_timing_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, int vunit)
+static void lcdc_timing_cfg(struct starfive_crtc *sf_crtc,
+			    struct drm_crtc_state *state, int vunit)
 {
 	int hpw, hbk, hfp, vpw, vbk, vfp;
+	u32 htiming, vtiming, hvwid;
 
 	//h-sync
 	int hsync_len = state->adjusted_mode.crtc_hsync_end - state->adjusted_mode.crtc_hsync_start;
@@ -119,9 +122,9 @@ void lcdc_timing_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state
 	LCDC_PRT(" %s : h-sync = %d, h-bp = %d, h-fp = %d", __func__, hsync_len, left_margin, right_margin);
 	LCDC_PRT(" %s : v-sync = %d, v-bp = %d, v-fp = %d", __func__, vsync_len, upper_margin, lower_margin);
 
-	int htiming = hbk | hfp << LCDC_RGB_HFP;
-	int vtiming = vbk | vfp << LCDC_RGB_VFP;
-	int hvwid = hpw | vpw << LCDC_RGB_VPW | vunit << LCDC_RGB_UNIT;
+	htiming = hbk | hfp << LCDC_RGB_HFP;
+	vtiming = vbk | vfp << LCDC_RGB_VFP;
+	hvwid = hpw | vpw << LCDC_RGB_VPW | vunit << LCDC_RGB_UNIT;
 
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_H_TMG, htiming);
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_V_TMG, vtiming);
@@ -133,19 +136,19 @@ void lcdc_timing_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state
 
 //? background size
 //lcdc_desize_cfg(sf_dev, sf_dev->display_info.xres-1, sf_dev->display_info.yres-1);
-void lcdc_desize_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
+static void lcdc_desize_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
 {
 	int hsize = state->adjusted_mode.crtc_hdisplay - 1;
 	int vsize = state->adjusted_mode.crtc_vdisplay - 1;
-	int sizecfg = hsize | vsize << LCDC_BG_VSIZE;
+	u32 sizecfg = hsize | vsize << LCDC_BG_VSIZE;
 
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_BACKGROUD, sizecfg);
 	LCDC_PRT("LCDC Dest H-Size: %d, V-Size: %d\n", hsize, vsize);
 }
 
-void lcdc_rgb_dclk_cfg(struct starfive_crtc *sf_crtc, int dot_clk_sel)
+static void lcdc_rgb_dclk_cfg(struct starfive_crtc *sf_crtc, int dot_clk_sel)
 {
-	int cfg = dot_clk_sel << 16;
+	u32 cfg = dot_clk_sel << 16;
 
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_DCLK, cfg);
 	LCDC_PRT("LCDC Dot_clock_output_sel: 0x%x\n", cfg);
@@ -155,14 +158,16 @@ void lcdc_rgb_dclk_cfg(struct starfive_crtc *sf_crtc, int dot_clk_sel)
 // color table
 //win0, no lock transfer
 //win3, no srcSel and addrMode, 0 assigned to them
-//lcdc_win_cfgA(sf_dev, winNum, sf_dev->display_info.xres-1, sf_dev->display_info.yres-1, 0x1, 0x0, 0x0, 0x1, 0x0, 0x0);
-void lcdc_win_cfgA(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, int winNum, int layEn, int clorTab,
-			int colorEn, int addrMode, int lock)
+//lcdc_win_cfgA(sf_dev, winNum, sf_dev->display_info.xres-1, sf_dev->display_info.yres-1,
+//		0x1, 0x0, 0x0, 0x1, 0x0, 0x0);
+static void lcdc_win_cfgA(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state,
+			  int winNum, int layEn, int clorTab,
+			  int colorEn, int addrMode, int lock)
 {
-	int cfg;
 	int hsize = state->adjusted_mode.crtc_hdisplay - 1;
 	int vsize = state->adjusted_mode.crtc_vdisplay - 1;
 	int srcSel_v = 1;
+	u32 cfg;
 
 	if (sf_crtc->pp_conn_lcdc < 0)
 		srcSel_v = 0;
@@ -177,12 +182,16 @@ void lcdc_win_cfgA(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state,
 		winNum, hsize, vsize, layEn, srcSel_v, addrMode);
 }
 
-
-void lcdc_win_cfgB(struct starfive_crtc *sf_crtc, int winNum, int xpos, int ypos, int argbOrd)
+static void lcdc_win_cfgB(struct starfive_crtc *sf_crtc,
+			  int winNum, int xpos, int ypos, int argbOrd)
 {
 	int win_format = sf_crtc->lcdcfmt;
-	int cfg = xpos | ypos << LCDC_WIN_VPOS | win_format << LCDC_WIN_FMT
-		       | argbOrd << LCDC_WIN_ARGB_ORDER;
+	u32 cfg;
+
+	cfg = xpos |
+		ypos << LCDC_WIN_VPOS |
+		win_format << LCDC_WIN_FMT |
+		argbOrd << LCDC_WIN_ARGB_ORDER;
 
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_B + winNum * 0xC, cfg);
 	LCDC_PRT("LCDC Win%d Xpos: %d, Ypos: %d, win_format: 0x%x, ARGB Order: 0x%x\n",
@@ -190,7 +199,7 @@ void lcdc_win_cfgB(struct starfive_crtc *sf_crtc, int winNum, int xpos, int ypos
 }
 
 //? Color key
-void lcdc_win_cfgC(struct starfive_crtc *sf_crtc, int winNum, int colorKey)
+static void lcdc_win_cfgC(struct starfive_crtc *sf_crtc, int winNum, int colorKey)
 {
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_C + winNum * 0xC, colorKey);
 	LCDC_PRT("LCDC Win%d Color Key: 0x%6x\n", winNum, colorKey);
@@ -198,7 +207,8 @@ void lcdc_win_cfgC(struct starfive_crtc *sf_crtc, int winNum, int colorKey)
 
 //? hsize
 //lcdc_win_srcSize(sf_dev, winNum, sf_dev->display_info.xres-1);
-void lcdc_win_srcSize(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, int winNum)
+static void lcdc_win_srcSize(struct starfive_crtc *sf_crtc,
+			     struct drm_crtc_state *state, int winNum)
 {
 	int addr, off, winsize, preCfg, cfg;
 	int hsize = state->adjusted_mode.crtc_hdisplay - 1;
@@ -256,27 +266,30 @@ void lcdc_win_srcSize(struct starfive_crtc *sf_crtc, struct drm_crtc_state *stat
 	LCDC_PRT("LCDC Win%d Src Hsize: %d\n", winNum, hsize);
 }
 
-void lcdc_alphaVal_cfg(struct starfive_crtc *sf_crtc, int val1, int val2, int val3, int val4, int sel)
+static void lcdc_alphaVal_cfg(struct starfive_crtc *sf_crtc,
+			      int val1, int val2, int val3, int val4, int sel)
 {
-	int val = val1 | val2 << LCDC_ALPHA2
-			| val3 << LCDC_ALPHA3
-			| val4 << LCDC_ALPHA4
-			| sel << LCDC_01_ALPHA_SEL;
-
-	int preVal = 0xfffb0000 & sf_fb_lcdcread32(sf_crtc, LCDC_ALPHA_VALUE);
+	u32 val = val1 |
+		val2 << LCDC_ALPHA2 |
+		val3 << LCDC_ALPHA3 |
+		val4 << LCDC_ALPHA4 |
+		sel << LCDC_01_ALPHA_SEL;
+	u32 preVal = sf_fb_lcdcread32(sf_crtc, LCDC_ALPHA_VALUE) & 0xfffb0000U;
 
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_ALPHA_VALUE, preVal | val);
 	LCDC_PRT("LCDC Alpha 1: %x, 2: %x, 3: %x, 4: %x\n", val1, val2, val3, val4);
 }
 
-void lcdc_panel_cfg(struct starfive_crtc *sf_crtc, int buswid, int depth, int txcycle, int pixpcycle,
-		int rgb565sel, int rgb888sel)
+static void lcdc_panel_cfg(struct starfive_crtc *sf_crtc,
+			   int buswid, int depth, int txcycle, int pixpcycle,
+			   int rgb565sel, int rgb888sel)
 {
-	int cfg = buswid | depth << LCDC_COLOR_DEP
-			| txcycle << LCDC_TCYCLES
-			| pixpcycle << LCDC_PIXELS
-			| rgb565sel << LCDC_565RGB_SEL
-			| rgb888sel << LCDC_888RGB_SEL;
+	u32 cfg = buswid |
+		depth << LCDC_COLOR_DEP |
+		txcycle << LCDC_TCYCLES |
+		pixpcycle << LCDC_PIXELS |
+		rgb565sel << LCDC_565RGB_SEL |
+		rgb888sel << LCDC_888RGB_SEL;
 
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_PANELDATAFMT, cfg);
 	LCDC_PRT("LCDC bus bit: :%d, pixDep: 0x%x, txCyle: %d, %dpix/cycle, RGB565 2cycle_%d, RGB888 3cycle_%d\n",
@@ -284,7 +297,7 @@ void lcdc_panel_cfg(struct starfive_crtc *sf_crtc, int buswid, int depth, int tx
 }
 
 //winNum: 0-2
-void lcdc_win02Addr_cfg(struct starfive_crtc *sf_crtc, int addr0, int addr1)
+static void lcdc_win02Addr_cfg(struct starfive_crtc *sf_crtc, int addr0, int addr1)
 {
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR0 + sf_crtc->winNum * 0x8, addr0);
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR1 + sf_crtc->winNum * 0x8, addr1);
@@ -295,27 +308,23 @@ void starfive_set_win_addr(struct starfive_crtc *sf_crtc, int addr)
 {
 	lcdc_win02Addr_cfg(sf_crtc, addr, 0x0);
 }
-EXPORT_SYMBOL(starfive_set_win_addr);
 
 void lcdc_enable_intr(struct starfive_crtc *sf_crtc)
 {
-	int cfg;
+	u32 cfg = ~(1U << LCDC_OUT_FRAME_END);
 
-	cfg = ~(0x1 << LCDC_OUT_FRAME_END);
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, cfg);
 }
-EXPORT_SYMBOL(lcdc_enable_intr);
 
 void lcdc_disable_intr(struct starfive_crtc *sf_crtc)
 {
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, 0xff);
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_CLR, 0xff);
 }
-EXPORT_SYMBOL(lcdc_disable_intr);
 
 int lcdc_win_sel(struct starfive_crtc *sf_crtc, enum lcdc_in_mode sel)
 {
-	int winNum = 2;
+	int winNum;
 
 	switch (sel) {
 	case LCDC_IN_LCD_AXI:
@@ -335,11 +344,12 @@ int lcdc_win_sel(struct starfive_crtc *sf_crtc, enum lcdc_in_mode sel)
 		winNum = LCDC_WIN_1;
 		//mapconv_pp0_sel(sf_dev, 0x1);
 		break;
+	default:
+		winNum = 2;
 	}
 
 	return winNum;
 }
-EXPORT_SYMBOL(lcdc_win_sel);
 
 void lcdc_dsi_sel(struct starfive_crtc *sf_crtc)
 {
@@ -354,38 +364,35 @@ void lcdc_dsi_sel(struct starfive_crtc *sf_crtc)
 	temp &= ~(0x1<<BIT_RST_DSI_DPI_PIX);
 	starfive_lcdc_rstwrite32(sf_crtc, SRST_ASSERT0, temp);
 }
-EXPORT_SYMBOL(lcdc_dsi_sel);
 
 irqreturn_t lcdc_isr_handler(int this_irq, void *dev_id)
 {
-	struct starfive_crtc *sf_crtc = (struct starfive_crtc *)dev_id;
-	static int count;
-	u32 intr_status = 0;
+	struct starfive_crtc *sf_crtc = dev_id;
+	//u32 intr_status = sf_fb_lcdcread32(sf_crtc, LCDC_INT_STATUS);
 
-	intr_status = sf_fb_lcdcread32(sf_crtc, LCDC_INT_STATUS);
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_CLR, 0xffffffff);
 
-	count++;
-	if (count % 100 == 0)
-		LCDC_PRT("lcdc count = %d, intr_status = 0x%x\n", count, intr_status);
 	return IRQ_HANDLED;
 }
-EXPORT_SYMBOL(lcdc_isr_handler);
 
 void lcdc_int_cfg(struct starfive_crtc *sf_crtc, int mask)
 {
-	int cfg;
+	u32 cfg;
 
 	if (mask == 0x1)
 		cfg = 0xffffffff;
 	else
-		cfg = ~(0x1 << LCDC_OUT_FRAME_END); //only frame end interrupt mask
+		cfg = ~(1U << LCDC_OUT_FRAME_END); //only frame end interrupt mask
+
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, cfg);
 }
-EXPORT_SYMBOL(lcdc_int_cfg);
 
 void lcdc_config(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, int winNum)
 {
+	struct drm_encoder *encoder = NULL;
+
+	encoder = starfive_head_atom_get_encoder(sf_crtc);
+
 	lcdc_mode_cfg(sf_crtc, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0);
 	lcdc_timing_cfg(sf_crtc, state, 0);
 	lcdc_desize_cfg(sf_crtc, state);
@@ -395,23 +402,26 @@ void lcdc_config(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, in
 		lcdc_win02Addr_cfg(sf_crtc, sf_crtc->dma_addr, 0x0);
 
 	lcdc_win_cfgA(sf_crtc, state, winNum, 0x1, 0x0, 0x0, 0x0, 0x0);
-	lcdc_win_cfgB(sf_crtc, winNum, 0x0, 0x0, 0x0);
+
+	if (encoder->encoder_type == DRM_MODE_ENCODER_DSI)
+		lcdc_win_cfgB(sf_crtc, winNum, 0x0, 0x0, 0x0);
+	else if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
+		lcdc_win_cfgB(sf_crtc, winNum, 0x0, 0x0, 0x1);
+
 	lcdc_win_cfgC(sf_crtc, winNum, 0xffffff);
 
 	lcdc_win_srcSize(sf_crtc, state, winNum);
 	lcdc_alphaVal_cfg(sf_crtc, 0xf, 0xf, 0xf, 0xf, 0x0);
 	lcdc_panel_cfg(sf_crtc, 0x3, 0x4, 0x0, 0x0, 0x0, 0x1);  //rgb888sel?
 }
-EXPORT_SYMBOL(lcdc_config);
 
 void lcdc_run(struct starfive_crtc *sf_crtc, uint32_t winMode, uint32_t lcdTrig)
 {
-	uint32_t runcfg = winMode << LCDC_EN_CFG_MODE | lcdTrig;
+	u32 runcfg = winMode << LCDC_EN_CFG_MODE | lcdTrig;
 
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_SWITCH, runcfg);
 	LCDC_PRT("Start run LCDC\n");
 }
-EXPORT_SYMBOL(lcdc_run);
 
 static int sf_fb_lcdc_clk_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
 {
@@ -452,7 +462,6 @@ static int sf_fb_lcdc_init(struct starfive_crtc *sf_crtc, struct drm_crtc_state
 
 int starfive_lcdc_enable(struct starfive_crtc *sf_crtc)
 {
-	int ret = 0;
 	struct drm_crtc_state *state = sf_crtc->crtc.state;
 
 	lcdc_disable_intr(sf_crtc);
@@ -462,23 +471,16 @@ int starfive_lcdc_enable(struct starfive_crtc *sf_crtc)
 		return -EINVAL;
 	}
 
-	//LCDC_PRT("encoder->encoder_type = %d\n",sf_crtc->encoder_type);
-	//if(DRM_MODE_ENCODER_DSI == sf_crtc->encoder_type)//2-TMDS, 3-LVDS, 6-DSI, 8-DPI
-	//	lcdc_dsi_sel(sf_crtc);
-
 	if (sf_fb_lcdc_init(sf_crtc, state)) {
 		dev_err(sf_crtc->dev, "lcdc init fail\n");
 		return -EINVAL;
 	}
 
 	lcdc_run(sf_crtc, sf_crtc->winNum, LCDC_RUN);
-
 	lcdc_enable_intr(sf_crtc);
 
-	return ret;
-
+	return 0;
 }
-EXPORT_SYMBOL(starfive_lcdc_enable);
 
 void starfive_lcdc_disable(struct starfive_crtc *sf_crtc)
 {
diff --git a/drivers/gpu/drm/starfive/starfive_drm_seeedpanel.c b/drivers/gpu/drm/starfive/starfive_drm_seeedpanel.c
index c1288483d567..3311e987cd47 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_seeedpanel.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_seeedpanel.c
@@ -383,13 +383,11 @@ static const struct drm_panel_funcs seeed_panel_funcs = {
 static int seeed_panel_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
 	u8 reg_value = 0;
-	int i;
 	struct seeed_panel_dev *seeed_panel;
 	struct device_node *endpoint, *dsi_host_node;
 	struct mipi_dsi_host *host;
 	struct device *dev = &client->dev;
 
-	int ver;
 	struct mipi_dsi_device_info info = {
 		.type = RPI_DSI_DRIVER_NAME,
 		.channel = 0, //0,
diff --git a/drivers/gpu/drm/starfive/starfive_drm_vpp.c b/drivers/gpu/drm/starfive/starfive_drm_vpp.c
index 01e075da29f9..5ecdd5e73662 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_vpp.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.c
@@ -1,18 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* driver/video/starfive/starfive_vpp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Copyright (C) 2020 StarFive, Inc.
- *
- * PURPOSE:	This files contains the driver of VPP.
- *
- * CHANGE HISTORY:
- *	Version		Date		Author		Description
- *	0.1.0		2020-10-09	starfive		created
- *
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
  */
 
 #include <linux/clk.h>
@@ -104,7 +92,6 @@ void mapconv_pp0_sel(struct starfive_crtc *sf_crtc, int sel)
 	temp |= (sel & 0x1);
 	sf_fb_syswrite32(sf_crtc, SYS_MAP_CONV, temp);
 }
-EXPORT_SYMBOL(mapconv_pp0_sel);
 
 void pp_output_cfg(struct starfive_crtc *sf_crtc, int ppNum, int outSel, int progInter, int desformat, int ptMode)
 {
@@ -231,7 +218,6 @@ void pp_desOffset_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yoff, int uo
 	PP_PRT("PP%d des-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n", ppNum, yoff, uoff, voff);
 }
 
-
 void pp_intcfg(struct starfive_crtc *sf_crtc, int ppNum, int intMask)
 {
 	int intcfg = ~(0x1<<0);
@@ -240,7 +226,6 @@ void pp_intcfg(struct starfive_crtc *sf_crtc, int ppNum, int intMask)
 		intcfg = 0xf;
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_MASK, intcfg);
 }
-EXPORT_SYMBOL(pp_intcfg);
 
 //next source frame Y/RGB start address, ?
 void pp_srcAddr_next(struct starfive_crtc *sf_crtc, int ppNum, int ysa, int usa, int vsa)
@@ -250,7 +235,6 @@ void pp_srcAddr_next(struct starfive_crtc *sf_crtc, int ppNum, int ysa, int usa,
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_V_SA_NXT, vsa);
 	PP_PRT("PP%d next Y startAddr: 0x%8x, U startAddr: 0x%8x, V startAddr: 0x%8x\n", ppNum, ysa, usa, vsa);
 }
-EXPORT_SYMBOL(pp_srcAddr_next);
 
 void pp_srcOffset_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yoff, int uoff, int voff)
 {
@@ -259,14 +243,12 @@ void pp_srcOffset_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yoff, int uo
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_V_OFS, voff);
 	PP_PRT("PP%d src-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n", ppNum, yoff, uoff, voff);
 }
-EXPORT_SYMBOL(pp_srcOffset_cfg);
 
 void pp_nxtAddr_load(struct starfive_crtc *sf_crtc, int ppNum, int nxtPar, int nxtPos)
 {
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_LOAD_NXT_PAR, nxtPar | nxtPos);
 	PP_PRT("PP%d next addrPointer: %d, %d set Regs\n", ppNum, nxtPar, nxtPos);
 }
-EXPORT_SYMBOL(pp_nxtAddr_load);
 
 void pp_run(struct starfive_crtc *sf_crtc, int ppNum, int start)
 {
@@ -274,13 +256,11 @@ void pp_run(struct starfive_crtc *sf_crtc, int ppNum, int start)
 	//if(start)
 	//  PP_PRT("Now start the PP%d\n\n", ppNum);
 }
-EXPORT_SYMBOL(pp_run);
 
 void pp1_enable_intr(struct starfive_crtc *sf_crtc)
 {
 	sf_fb_vppwrite32(sf_crtc, 1, PP_INT_MASK, 0x0);
 }
-EXPORT_SYMBOL(pp1_enable_intr);
 
 void pp_enable_intr(struct starfive_crtc *sf_crtc, int ppNum)
 {
@@ -288,64 +268,54 @@ void pp_enable_intr(struct starfive_crtc *sf_crtc, int ppNum)
 
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_MASK, cfg);
 }
-EXPORT_SYMBOL(pp_enable_intr);
 
 void pp_disable_intr(struct starfive_crtc *sf_crtc, int ppNum)
 {
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_MASK, 0xf);
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_CLR, 0xf);
 }
-EXPORT_SYMBOL(pp_disable_intr);
 
 static void pp_srcfmt_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *src)
 {
 	switch (src->format) {
 	case COLOR_YUV422_YVYU:
-		PP_INFO("src_format: COLOR_YUV422_YVYU\n");
 		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_YVYU, 0x0, 0x0);
 		break;
 	case COLOR_YUV422_VYUY:
-		PP_INFO("src_format: COLOR_YUV422_VYUY\n");
 		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_VYUY, 0x0, 0x0);
 		break;
 	case COLOR_YUV422_YUYV:
-		PP_INFO("src_format: COLOR_YUV422_YUYV\n");
 		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_YUYV, 0x0, 0x0);
 		break;
 	case COLOR_YUV422_UYVY:
-		PP_INFO("src_format: COLOR_YUV422_UYVY\n");
 		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_UYVY, 0x0, 0x0);
 		break;
 	case COLOR_YUV420P:
-		PP_INFO("src_format: COLOR_YUV420P\n");
 		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420P, 0x0, 0, 0x0, 0x0);
 		break;
 	case COLOR_YUV420_NV12:
-		PP_INFO("src_format: COLOR_YUV420_NV12\n");
 		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420I, 0x1, 0, COLOR_YUV420_NV12-COLOR_YUV420_NV12, 0x0);
 		break;
 	case COLOR_YUV420_NV21:
-		PP_INFO("src_format: COLOR_YUV420_NV21\n");
 		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420I, 0x1, 0, COLOR_YUV420_NV21-COLOR_YUV420_NV12, 0x0);
 		break;
 	case COLOR_RGB888_ARGB:
-		PP_INFO("src_format: COLOR_RGB888_ARGB\n");
-		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_ARGB-COLOR_RGB888_ARGB);//0x0);
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0,
+				0x0, COLOR_RGB888_ARGB - COLOR_RGB888_ARGB);
 		break;
 	case COLOR_RGB888_ABGR:
-		PP_INFO("src_format: COLOR_RGB888_ABGR\n");
-		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_ABGR-COLOR_RGB888_ARGB);//0x1);
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0,
+				0x0, COLOR_RGB888_ABGR-COLOR_RGB888_ARGB);
 		break;
 	case COLOR_RGB888_RGBA:
-		PP_INFO("src_format: COLOR_RGB888_RGBA\n");
-		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_RGBA-COLOR_RGB888_ARGB);//0x2);
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0,
+				0x0, COLOR_RGB888_RGBA-COLOR_RGB888_ARGB);
 		break;
 	case COLOR_RGB888_BGRA:
-		PP_INFO("src_format: COLOR_RGB888_BGRA\n");
-		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_BGRA-COLOR_RGB888_ARGB);//0x3);
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0,
+				0x0, COLOR_RGB888_BGRA-COLOR_RGB888_ARGB);
 		break;
 	case COLOR_RGB565:
-		PP_INFO("src_format: COLOR_RGB888_RGB565\n");
 		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_RGB565, 0x0, 0x0, 0x0, 0x0);
 		break;
 	}
@@ -360,70 +330,58 @@ static void pp_dstfmt_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_vi
 
 	switch (dst->format) {
 	case COLOR_YUV422_YVYU:
-		PP_INFO("dst_format: COLOR_YUV422_YVYU\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
 		break;
 	case COLOR_YUV422_VYUY:
-		PP_INFO("dst_format: COLOR_YUV422_VYUY\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_VYUY);
 		break;
 	case COLOR_YUV422_YUYV:
-		PP_INFO("dst_format: COLOR_YUV422_YUYV\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YUYV);
 		break;
 	case COLOR_YUV422_UYVY:
-		PP_INFO("dst_format: COLOR_YUV422_UYVY\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
 		break;
 	case COLOR_YUV420P:
-		PP_INFO("dst_format: COLOR_YUV420P\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420P, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
 		break;
 	case COLOR_YUV420_NV12:
-		PP_INFO("dst_format: COLOR_YUV420_NV21\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420I, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, COLOR_YUV420_NV12 - COLOR_YUV420_NV12, 0);
 		break;
 	case COLOR_YUV420_NV21:
-		PP_INFO("dst_format: COLOR_YUV420_NV12\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420I, 0x0);///0x2, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, COLOR_YUV420_NV21 - COLOR_YUV420_NV12, 0);
 		break;
 	case COLOR_RGB888_ARGB:
-		PP_INFO("dst_format: COLOR_RGB888_ARGB\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_ARGB888, 0x0);
 		//pp_output_fmt_cfg(ppNum, 0, 0);
 		break;
 	case COLOR_RGB888_ABGR:
-		PP_INFO("dst_format: COLOR_RGB888_ABGR\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_ABGR888, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
 		break;
 	case COLOR_RGB888_RGBA:
-		PP_INFO("dst_format: COLOR_RGB888_RGBA\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_RGBA888, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
 		break;
 	case COLOR_RGB888_BGRA:
-		PP_INFO("dst_format: COLOR_RGB888_BGRA\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_BGRA888, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
 		break;
 	case COLOR_RGB565:
-		PP_INFO("dst_format: COLOR_RGB565\n");
 		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_RGB565, 0x0);
 		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
 		break;
 	}
 }
 
-
-void pp_format_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *src, struct pp_video_mode *dst)
+static void pp_format_set(struct starfive_crtc *sf_crtc, int ppNum,
+		   struct pp_video_mode *src, struct pp_video_mode *dst)
 {
 	/* 1:bypass, 0:not bypass */
 	unsigned int scale_byp = 1;
@@ -431,7 +389,7 @@ void pp_format_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mod
 	pp_srcfmt_set(sf_crtc, ppNum, src);
 	pp_dstfmt_set(sf_crtc, ppNum, dst);
 
-	if ((src->height != dst->height) || (src->width != dst->width))
+	if (src->height != dst->height || src->width != dst->width)
 		scale_byp = 0;
 
 	if ((src->format >= COLOR_RGB888_ARGB) && (dst->format <= COLOR_YUV420_NV21)) {
@@ -461,9 +419,10 @@ void pp_format_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mod
 	pp_int_interval_cfg(sf_crtc, ppNum, 0x1);
 }
 
-void pp_size_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *src, struct pp_video_mode *dst)
+static void pp_size_set(struct starfive_crtc *sf_crtc, int ppNum,
+			struct pp_video_mode *src, struct pp_video_mode *dst)
 {
-	uint32_t srcAddr, dstaddr;
+	u32 srcAddr, dstaddr;
 	unsigned int size, y_rgb_ofst, uofst;
 	unsigned int v_uvofst = 0, next_y_rgb_addr = 0, next_u_addr = 0, next_v_addr = 0;
 	unsigned int i = 0;
@@ -612,11 +571,10 @@ void pp_size_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode
 		pp_desAddr_cfg(sf_crtc, ppNum, next_y_rgb_addr, next_u_addr, next_v_addr);
 		pp_desOffset_cfg(sf_crtc, ppNum, y_rgb_ofst, uofst, v_uvofst);
 	}
-
 }
 
-
-static void pp_config(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *src, struct pp_video_mode *dst)
+static void pp_config(struct starfive_crtc *sf_crtc, int ppNum,
+		      struct pp_video_mode *src, struct pp_video_mode *dst)
 {
 	//pp_disable_intr(sf_dev, ppNum);
 	pp_format_set(sf_crtc, ppNum, src, dst);
@@ -625,19 +583,14 @@ static void pp_config(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_
 
 irqreturn_t vpp1_isr_handler(int this_irq, void *dev_id)
 {
-	struct starfive_crtc *sf_crtc = (struct starfive_crtc *)dev_id;
-	static int count;
+	struct starfive_crtc *sf_crtc = dev_id;
 	u32 intr_status = 0;
 
 	intr_status = sf_fb_vppread32(sf_crtc, 1, PP_INT_STATUS);
 	sf_fb_vppwrite32(sf_crtc, 1, PP_INT_CLR, 0xf);
 
-	count++;
-
 	return IRQ_HANDLED;
 }
-EXPORT_SYMBOL(vpp1_isr_handler);
-
 
 static void starfive_pp_enable_intr(struct starfive_crtc *sf_crtc, int enable)
 {
@@ -653,15 +606,17 @@ static void starfive_pp_enable_intr(struct starfive_crtc *sf_crtc, int enable)
 	}
 }
 
-static int starfive_pp_video_mode_init(struct starfive_crtc *sf_crtc, struct pp_video_mode *src,
-		struct pp_video_mode *dst, int pp_id)
+static int starfive_pp_video_mode_init(struct starfive_crtc *sf_crtc,
+				       struct pp_video_mode *src,
+				       struct pp_video_mode *dst,
+				       int pp_id)
 {
-	if ((!src) || (!dst)) {
+	if (!src || !dst) {
 		dev_err(sf_crtc->dev, "Invalid argument!\n");
 		return -EINVAL;
 	}
 
-	if ((pp_id < PP_NUM) && (pp_id >= 0)) {
+	if (pp_id < PP_NUM && pp_id >= 0) {
 		src->format = sf_crtc->vpp_format;
 		src->width = sf_crtc->crtc.state->adjusted_mode.hdisplay;
 		src->height = sf_crtc->crtc.state->adjusted_mode.vdisplay;
@@ -723,9 +678,7 @@ int starfive_pp_enable(struct starfive_crtc *sf_crtc)
 	starfive_pp_enable_intr(sf_crtc, PP_INTR_ENABLE);
 
 	return 0;
-
 }
-EXPORT_SYMBOL(starfive_pp_enable);
 
 int starfive_pp_update(struct starfive_crtc *sf_crtc)
 {
@@ -745,10 +698,7 @@ int starfive_pp_update(struct starfive_crtc *sf_crtc)
 	}
 
 	return 0;
-
 }
-EXPORT_SYMBOL(starfive_pp_update);
-
 
 int starfive_pp_get_2lcdc_id(struct starfive_crtc *sf_crtc)
 {
@@ -766,7 +716,6 @@ int starfive_pp_get_2lcdc_id(struct starfive_crtc *sf_crtc)
 
 	return -ENODEV;
 }
-EXPORT_SYMBOL(starfive_pp_get_2lcdc_id);
 
 void dsitx_vout_init(struct starfive_crtc *sf_crtc)
 {
@@ -779,16 +728,16 @@ void dsitx_vout_init(struct starfive_crtc *sf_crtc)
 	reset_control_deassert(sf_crtc->rst_vout_src);
 	reset_control_deassert(sf_crtc->rst_disp_axi);
 
-	sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, BIT(31), BIT(31));
 
 	sf_set_clear(sf_crtc->base_rst, vout_rstgen_assert0_REG, ~0x1981ec, 0x1981ec);
 
@@ -797,7 +746,6 @@ void dsitx_vout_init(struct starfive_crtc *sf_crtc)
 		temp &= 0x1981ec;
 	} while (temp != 0x1981ec);
 }
-EXPORT_SYMBOL(dsitx_vout_init);
 
 void vout_reset(struct starfive_crtc *sf_crtc)
 {
@@ -810,22 +758,22 @@ void vout_reset(struct starfive_crtc *sf_crtc)
 	reset_control_deassert(sf_crtc->rst_vout_src);
 	reset_control_deassert(sf_crtc->rst_disp_axi);
 
-	sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_mapconv_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_mapconv_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_pixrawout_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_pixrawout_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_pixclk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
-	sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_mapconv_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_mapconv_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_pixrawout_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_pixrawout_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_pixclk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, BIT(31), BIT(31));
 
 	sf_set_clear(sf_crtc->base_rst, vout_rstgen_assert0_REG, ~0x19bfff, 0x19bfff);
 
@@ -833,9 +781,7 @@ void vout_reset(struct starfive_crtc *sf_crtc)
 		temp = ioread32(sf_crtc->base_rst + vout_rstgen_status0_REG);
 		temp &= 0x19bfff;
 	} while (temp != 0x19bfff);
-
 }
-EXPORT_SYMBOL(vout_reset);
 
 void vout_disable(struct starfive_crtc *sf_crtc)
 {
@@ -846,8 +792,6 @@ void vout_disable(struct starfive_crtc *sf_crtc)
 	reset_control_assert(sf_crtc->rst_vout_src);
 	reset_control_assert(sf_crtc->rst_disp_axi);
 }
-EXPORT_SYMBOL(vout_disable);
-
 
 MODULE_AUTHOR("StarFive Technology Co., Ltd.");
 MODULE_DESCRIPTION("loadable VPP driver for StarFive");