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authorXingyu Wu <xingyu.wu@starfivetech.com>2023-10-17 12:22:52 +0300
committerHal Feng <hal.feng@starfivetech.com>2024-03-05 10:18:27 +0300
commit2fef0872da3893e4646d19245fd4463c8128b078 (patch)
tree7656eeb1f5f7a5c6ad6438a3133d9836145e414a
parent29ebe44f04a92b477aa25a473c1a95788e4eb98c (diff)
downloadlinux-2fef0872da3893e4646d19245fd4463c8128b078.tar.xz
ASoC: dwc: i2s: Add RX master support for StarFive JH7110 SoC
Add JH7110 I2S RX master support, so the PDM can work on JH7110 EVB board. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
-rwxr-xr-x[-rw-r--r--]sound/soc/dwc/dwc-i2s.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c
index a25ffe50d5c1..d349841280d6 100644..100755
--- a/sound/soc/dwc/dwc-i2s.c
+++ b/sound/soc/dwc/dwc-i2s.c
@@ -906,6 +906,27 @@ static int jh7110_i2srx_crg_init(struct dw_i2s_dev *dev)
return jh7110_i2s_crg_slave_init(dev);
}
+/* Special syscon initialization about RX channel with master mode on JH7110 SoC */
+static int jh7110_i2srx_mst_crg_init(struct dw_i2s_dev *dev)
+{
+ struct regmap *regmap;
+ unsigned int args[5];
+
+ regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node,
+ "starfive,syscon",
+ 5, args);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n");
+
+ /* Enable I2Srx with syscon register, args[0]: offset, args[1]: mask */
+ regmap_update_bits(regmap, args[0], args[1], args[1]);
+
+ /* Change I2Srx source (PDM) with syscon register, args[0]: offset, args[1]: mask */
+ regmap_update_bits(regmap, args[2], args[3], args[4]);
+
+ return jh7110_i2s_crg_master_init(dev);
+}
+
static int jh7110_i2stx0_clk_cfg(struct i2s_clk_config_data *config)
{
struct dw_i2s_dev *dev = container_of(config, struct dw_i2s_dev, config);
@@ -1086,11 +1107,21 @@ static const struct i2s_platform_data jh7110_i2srx_data = {
.i2s_pd_init = jh7110_i2srx_crg_init,
};
+static const struct i2s_platform_data jh7110_i2srx_mst_data = {
+ .cap = DWC_I2S_RECORD | DW_I2S_MASTER,
+ .channel = TWO_CHANNEL_SUPPORT,
+ .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
+ .snd_rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000,
+ .i2s_clk_cfg = jh7110_i2stx0_clk_cfg,
+ .i2s_pd_init = jh7110_i2srx_mst_crg_init,
+};
+
static const struct of_device_id dw_i2s_of_match[] = {
{ .compatible = "snps,designware-i2s", },
{ .compatible = "starfive,jh7110-i2stx0", .data = &jh7110_i2stx0_data, },
{ .compatible = "starfive,jh7110-i2stx1", .data = &jh7110_i2stx1_data,},
{ .compatible = "starfive,jh7110-i2srx", .data = &jh7110_i2srx_data,},
+ { .compatible = "starfive,jh7110-i2srx-master", .data = &jh7110_i2srx_mst_data,},
{},
};