diff options
| author | Eric Lin <eric.lin@sifive.com> | 2025-02-13 04:21:39 +0300 |
|---|---|---|
| committer | Namhyung Kim <namhyung@kernel.org> | 2025-03-11 00:15:38 +0300 |
| commit | 2e3a13d6b74ee0ca59b2243878b7b6e0dddbcf6b (patch) | |
| tree | 3e5d3e5068a0eee787d63f274a5d9ed4bf875497 | |
| parent | 8866a33815507485f8129b395511b8b2a0f6411d (diff) | |
| download | linux-2e3a13d6b74ee0ca59b2243878b7b6e0dddbcf6b.tar.xz | |
perf vendor events riscv: Add SiFive P550 events
The SiFive Performance P550 core features an out-of-order
microarchitecture which exposes the same PMU events as Bullet,
plus events for UTLB hits and PTE cache misses/hits.
Add support for specifying these events using symbolic names.
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Tested-by: Ian Rogers <irogers@google.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20250213220341.3215660-7-samuel.holland@sifive.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
5 files changed, 51 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index 9e9bd7ac0ebe..a301e9dbfd5a 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -17,6 +17,7 @@ 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core 0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core 0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core +0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core 0x5b7-0x0-0x0,v1,thead/c900-legacy,core 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json new file mode 120000 index 000000000000..34e5c2870eee --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json @@ -0,0 +1 @@ +../bullet/firmware.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json new file mode 120000 index 000000000000..62eacc2d7497 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json @@ -0,0 +1 @@ +../bullet/instruction.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json new file mode 100644 index 000000000000..8393f81b2cf0 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json @@ -0,0 +1,47 @@ +[ + { + "EventName": "ICACHE_MISS", + "EventCode": "0x102", + "BriefDescription": "Counts instruction cache misses" + }, + { + "EventName": "DCACHE_MISS", + "EventCode": "0x202", + "BriefDescription": "Counts data cache misses" + }, + { + "EventName": "DCACHE_RELEASE", + "EventCode": "0x402", + "BriefDescription": "Counts writeback requests from the data cache" + }, + { + "EventName": "ITLB_MISS", + "EventCode": "0x802", + "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests" + }, + { + "EventName": "DTLB_MISS", + "EventCode": "0x1002", + "BriefDescription": "Counts Data TLB misses caused by data address translation requests" + }, + { + "EventName": "UTLB_MISS", + "EventCode": "0x2002", + "BriefDescription": "Counts Unified TLB misses caused by address translation requests" + }, + { + "EventName": "UTLB_HIT", + "EventCode": "0x4002", + "BriefDescription": "Counts Unified TLB hits for address translation requests" + }, + { + "EventName": "PTE_CACHE_MISS", + "EventCode": "0x8002", + "BriefDescription": "Counts Page Table Entry cache misses" + }, + { + "EventName": "PTE_CACHE_HIT", + "EventCode": "0x10002", + "BriefDescription": "Counts Page Table Entry cache hits" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json new file mode 120000 index 000000000000..ba5dd2960e9f --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json @@ -0,0 +1 @@ +../bullet/microarch.json
\ No newline at end of file |