diff options
| author | J. Neuschäfer <j.ne@posteo.net> | 2024-12-24 11:02:12 +0300 |
|---|---|---|
| committer | Bartosz Golaszewski <bartosz.golaszewski@linaro.org> | 2025-01-13 11:20:25 +0300 |
| commit | 267f2c5662e3fd8891bca01f71bc1c258e293206 (patch) | |
| tree | e0bd712a4dc8f7e1b00c533766418e86d3a3195d | |
| parent | c9ec045fa8053820573efbaa70137d0857e444db (diff) | |
| download | linux-267f2c5662e3fd8891bca01f71bc1c258e293206.tar.xz | |
dt-bindings: gpio: fairchild,74hc595: Document chip select vs. latch clock
From looking at the data sheets, it is not obvious that CS# and latch
clock can be treated at the same, but doing so works fine and saves the
hassle of (1) trying to specify a SPI device without CS, and (2) adding
another property to drive the latch clock[1].
[1]: https://lore.kernel.org/lkml/20241213-gpio74-v1-2-fa2c089caf41@posteo.net/
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241224-gpio74-v2-3-bbcf14183191@posteo.net
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml index e8bc9f018edb..0e5c22929bde 100644 --- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml +++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml @@ -6,6 +6,23 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic 8-bit shift register +description: | + NOTE: These chips nominally don't have a chip select pin. They do however + have a rising-edge triggered latch clock (or storage register clock) pin, + which behaves like an active-low chip select. + + After the bits are shifted into the shift register, CS# is driven high, which + the 74HC595 sees as a rising edge on the latch clock that results in a + transfer of the bits from the shift register to the storage register and thus + to the output pins. + _ _ _ _ + shift clock ____| |_| |_..._| |_| |_________ + + latch clock * trigger + ___ ________ + chip select# |___________________| + + maintainers: - Maxime Ripard <mripard@kernel.org> |