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| author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2021-10-29 13:39:04 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-11-23 08:51:53 +0300 |
| commit | 25bba42f95f6ad22295c5a0204086ace9bff1e4a (patch) | |
| tree | 55fea641c6a838b88bc022c9f58b6dcadd10ec30 | |
| parent | 1c1597c8027aa4a98a56e8b5b341ddc38451f0e8 (diff) | |
| download | linux-25bba42f95f6ad22295c5a0204086ace9bff1e4a.tar.xz | |
phy: uniphier-pcie: Set VCOPLL clamp mode in PHY register
Set VCOPLL clamp mode to mode 0 to avoid hardware unstable issue.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1635503947-18250-6-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | drivers/phy/socionext/phy-uniphier-pcie.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c index fde8aac5f4b6..2bd8df619712 100644 --- a/drivers/phy/socionext/phy-uniphier-pcie.c +++ b/drivers/phy/socionext/phy-uniphier-pcie.c @@ -51,6 +51,9 @@ #define PCL_PHY_R26 26 #define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */ #define VCO_CTRL_INIT_VAL 5 +#define PCL_PHY_R28 28 +#define VCOPLL_CLMP GENMASK(3, 2) /* Tx VCOPLL clamp mode */ +#define VCOPLL_CLMP_VAL 0 struct uniphier_pciephy_priv { void __iomem *base; @@ -158,6 +161,8 @@ static int uniphier_pciephy_init(struct phy *phy) FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL)); uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL, FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL)); + uniphier_pciephy_set_param(priv, PCL_PHY_R28, VCOPLL_CLMP, + FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL)); usleep_range(1, 10); uniphier_pciephy_deassert(priv); |