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| author | Dmitry Osipenko <digetx@gmail.com> | 2020-11-04 19:48:40 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2020-11-05 22:35:37 +0300 |
| commit | 21d3cdd0391bb01b348a47ec117eff3b9615d3a9 (patch) | |
| tree | d782b2abdf564e5868e1b0a7fea47443523da813 | |
| parent | 65abc8ef57009b95fcded5136aed8ccaff46b903 (diff) | |
| download | linux-21d3cdd0391bb01b348a47ec117eff3b9615d3a9.tar.xz | |
dt-bindings: memory: tegra20: emc: Correct registers range in example
There is superfluous zero in the registers base address and registers
size should be twice bigger.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201104164923.21238-5-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index add95367640b..567cffd37f3f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -21,7 +21,7 @@ Example: #address-cells = < 1 >; #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; - reg = <0x7000f4000 0x200>; + reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; } |