diff options
| author | Emil Renner Berthing <emil.renner.berthing@canonical.com> | 2022-10-20 11:38:54 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-10-22 15:14:47 +0300 |
| commit | 0d814000ad3589bf4f69c9cb25a3b77bbd55ffec (patch) | |
| tree | 5722dbef172463ff8478fdc1bc2e4d96ae9435e8 | |
| parent | 6863aaa88516292b885fdce5dd91925a00c3a3de (diff) | |
| download | linux-0d814000ad3589bf4f69c9cb25a3b77bbd55ffec.tar.xz | |
riscv: dts: microchip: icicle: Add GPIO controlled LEDs
Add the 4 GPIO controlled LEDs to the Microchip PolarFire-SoC Icicle
Kit device tree. The schematic doesn't specify any special function
for the LEDs, so they're added here without any default triggers and
named led1, led2, led3 and led4 just like in the schematic.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index c3cb53f7059c..b04e3ff044b0 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -5,6 +5,8 @@ #include "mpfs.dtsi" #include "mpfs-icicle-kit-fabric.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 @@ -31,6 +33,34 @@ timebase-frequency = <RTCCLK_FREQ>; }; + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + label = "led1"; + }; + + led-2 { + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + label = "led2"; + }; + + led-3 { + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_AMBER>; + label = "led3"; + }; + + led-4 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_AMBER>; + label = "led4"; + }; + }; + ddrc_cache_lo: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; |