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Diffstat (limited to 'doc/src/libmcpu-psw-table.tex')
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diff --git a/doc/src/libmcpu-psw-table.tex b/doc/src/libmcpu-psw-table.tex new file mode 100644 index 0000000..579e2d2 --- /dev/null +++ b/doc/src/libmcpu-psw-table.tex @@ -0,0 +1,31 @@ +\begin{longtable}{@{}L{27mm}L{18mm}L{114mm}@{}} +\toprule +\textbf{Selector} & \textbf{Bit} & \textbf{Смысл для JSET/JCLR и PSW}\\ +\midrule +\endfirsthead +\toprule +\textbf{Selector} & \textbf{Bit} & \textbf{Смысл для JSET/JCLR и PSW}\\ +\midrule +\endhead +AF & 0 & CPU arithmetic auxiliary/carry state; writable by \code{SETF/CLRF}\\ +CF & 1 & CPU carry/borrow flag; writable by \code{SETF/CLRF}\\ +OF & 2 & CPU integer overflow flag; writable by \code{SETF/CLRF}\\ +SF & 3 & CPU sign flag; writable by \code{SETF/CLRF}\\ +PF & 4 & CPU parity/auxiliary result classification flag; writable by \code{SETF/CLRF}\\ +ZF & 5 & CPU zero flag; writable by \code{SETF/CLRF}\\ +RF & 6 & CPU-visible LibMPU arithmetic status flag; writable by \code{SETF/CLRF}\\ +VF & 7 & CPU-visible LibMPU value/validity status flag; writable by \code{SETF/CLRF}\\ +DOMF & 8 & MPU math domain error state; writable by \code{SETF/CLRF}\\ +SNGF & 9 & MPU singularity error state; writable by \code{SETF/CLRF}\\ +OVFF & 10 & MPU floating/math overflow state; writable by \code{SETF/CLRF}\\ +UDFF & 11 & MPU floating/math underflow state; writable by \code{SETF/CLRF}\\ +TLSF & 12 & MPU total-loss-of-significance state; writable by \code{SETF/CLRF}\\ +PLSF & 13 & MPU partial-loss-of-significance state; writable by \code{SETF/CLRF}\\ +INDF & 14 & MPU invalid/indeterminate state; writable by \code{SETF/CLRF}\\ +INXF & 15 & MPU inexact state; writable by \code{SETF/CLRF}\\ +HF & 16 & HALT-related execution state; readable by \code{JSET/JCLR}, not writable by \code{SETF/CLRF}\\ +TF & 17 & trace/trap control state; readable by \code{JSET/JCLR}, not writable by \code{SETF/CLRF}\\ +IF & 18 & interrupt-enable control state; readable by \code{JSET/JCLR}, not writable by \code{SETF/CLRF}\\ +\bottomrule +\end{longtable} +\noindent Поле MODE является многобитным и намеренно не имеет selector для \code{JSET/JCLR}. Архитектурно PSW[7:0] образует CPU flag byte, PSW[15:8] --- MPU flag byte. \code{SETF/CLRF} разрешают запись только selectors 0..15; \code{CLRCPUF} очищает PSW[7:0], \code{CLRMPUF} --- PSW[15:8]. HF/TF/IF/MODE этими инструкциями не изменяются. Точные правила изменения PSW конкретными арифметическими и conversion instructions описаны в основной части руководства. |