blob: b9364f6a4f8fec2ca7ae8df142a991e39d99e4ae (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
|
/* SPDX-License-Identifier: GPL-2.0 */
/* Microchip LAN937X switch register definitions
* Copyright (C) 2019-2021 Microchip Technology Inc.
*/
#ifndef __LAN937X_REG_H
#define __LAN937X_REG_H
#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
/* 0 - Operation */
#define REG_GLOBAL_CTRL_0 0x0007
#define SW_PHY_REG_BLOCK BIT(7)
#define SW_FAST_MODE BIT(3)
#define SW_FAST_MODE_OVERRIDE BIT(2)
#define REG_SW_INT_STATUS__4 0x0010
#define REG_SW_INT_MASK__4 0x0014
#define LUE_INT BIT(31)
#define TRIG_TS_INT BIT(30)
#define APB_TIMEOUT_INT BIT(29)
#define OVER_TEMP_INT BIT(28)
#define HSR_INT BIT(27)
#define PIO_INT BIT(26)
#define POR_READY_INT BIT(25)
#define SWITCH_INT_MASK \
(LUE_INT | TRIG_TS_INT | APB_TIMEOUT_INT | OVER_TEMP_INT | HSR_INT | \
PIO_INT | POR_READY_INT)
#define REG_SW_PORT_INT_STATUS__4 0x0018
#define REG_SW_PORT_INT_MASK__4 0x001C
/* 1 - Global */
#define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103
#define SW_CLK125_ENB BIT(1)
#define SW_CLK25_ENB BIT(0)
/* 3 - Operation Control */
#define REG_SW_OPERATION 0x0300
#define SW_DOUBLE_TAG BIT(7)
#define SW_OVER_TEMP_ENABLE BIT(2)
#define SW_RESET BIT(1)
#define REG_SW_LUE_CTRL_0 0x0310
#define SW_VLAN_ENABLE BIT(7)
#define SW_DROP_INVALID_VID BIT(6)
#define SW_AGE_CNT_M 0x7
#define SW_AGE_CNT_S 3
#define SW_RESV_MCAST_ENABLE BIT(2)
#define REG_SW_LUE_CTRL_1 0x0311
#define UNICAST_LEARN_DISABLE BIT(7)
#define SW_FLUSH_STP_TABLE BIT(5)
#define SW_FLUSH_MSTP_TABLE BIT(4)
#define SW_SRC_ADDR_FILTER BIT(3)
#define SW_AGING_ENABLE BIT(2)
#define SW_FAST_AGING BIT(1)
#define SW_LINK_AUTO_AGING BIT(0)
#define REG_SW_MAC_CTRL_0 0x0330
#define SW_NEW_BACKOFF BIT(7)
#define SW_PAUSE_UNH_MODE BIT(1)
#define SW_AGGR_BACKOFF BIT(0)
#define REG_SW_MAC_CTRL_1 0x0331
#define SW_SHORT_IFG BIT(7)
#define MULTICAST_STORM_DISABLE BIT(6)
#define SW_BACK_PRESSURE BIT(5)
#define FAIR_FLOW_CTRL BIT(4)
#define NO_EXC_COLLISION_DROP BIT(3)
#define SW_LEGAL_PACKET_DISABLE BIT(1)
#define SW_PASS_SHORT_FRAME BIT(0)
#define REG_SW_MAC_CTRL_6 0x0336
#define SW_MIB_COUNTER_FLUSH BIT(7)
#define SW_MIB_COUNTER_FREEZE BIT(6)
/* 4 - LUE */
#define REG_SW_ALU_STAT_CTRL__4 0x041C
#define REG_SW_ALU_VAL_B 0x0424
#define ALU_V_OVERRIDE BIT(31)
#define ALU_V_USE_FID BIT(30)
#define ALU_V_PORT_MAP 0xFF
/* 7 - VPhy */
#define REG_VPHY_IND_ADDR__2 0x075C
#define REG_VPHY_IND_DATA__2 0x0760
#define REG_VPHY_IND_CTRL__2 0x0768
#define VPHY_IND_WRITE BIT(1)
#define VPHY_IND_BUSY BIT(0)
#define REG_VPHY_SPECIAL_CTRL__2 0x077C
#define VPHY_SMI_INDIRECT_ENABLE BIT(15)
#define VPHY_SW_LOOPBACK BIT(14)
#define VPHY_MDIO_INTERNAL_ENABLE BIT(13)
#define VPHY_SPI_INDIRECT_ENABLE BIT(12)
#define VPHY_PORT_MODE_M 0x3
#define VPHY_PORT_MODE_S 8
#define VPHY_MODE_RGMII 0
#define VPHY_MODE_MII_PHY 1
#define VPHY_MODE_SGMII 2
#define VPHY_MODE_RMII_PHY 3
#define VPHY_SW_COLLISION_TEST BIT(7)
#define VPHY_SPEED_DUPLEX_STAT_M 0x7
#define VPHY_SPEED_DUPLEX_STAT_S 2
#define VPHY_SPEED_1000 BIT(4)
#define VPHY_SPEED_100 BIT(3)
#define VPHY_FULL_DUPLEX BIT(2)
/* Port Registers */
/* 0 - Operation */
#define REG_PORT_CTRL_0 0x0020
#define PORT_MAC_LOOPBACK BIT(7)
#define PORT_MAC_REMOTE_LOOPBACK BIT(6)
#define PORT_K2L_INSERT_ENABLE BIT(5)
#define PORT_K2L_DEBUG_ENABLE BIT(4)
#define PORT_TAIL_TAG_ENABLE BIT(2)
#define PORT_QUEUE_SPLIT_ENABLE 0x3
/* 1 - Phy */
#define REG_PORT_T1_PHY_CTRL_BASE 0x0100
/* 3 - xMII */
#define REG_PORT_XMII_CTRL_0 0x0300
#define PORT_SGMII_SEL BIT(7)
#define PORT_MII_FULL_DUPLEX BIT(6)
#define PORT_MII_TX_FLOW_CTRL BIT(5)
#define PORT_MII_RX_FLOW_CTRL BIT(3)
#define PORT_GRXC_ENABLE BIT(0)
#define REG_PORT_XMII_CTRL_1 0x0301
#define PORT_MII_SEL_EDGE BIT(5)
#define PORT_RGMII_ID_IG_ENABLE BIT(4)
#define PORT_RGMII_ID_EG_ENABLE BIT(3)
#define PORT_MII_MAC_MODE BIT(2)
#define PORT_MII_SEL_M 0x3
#define PORT_RGMII_SEL 0x0
#define PORT_RMII_SEL 0x1
#define PORT_MII_SEL 0x2
/* 4 - MAC */
#define REG_PORT_MAC_CTRL_0 0x0400
#define PORT_CHECK_LENGTH BIT(2)
#define PORT_BROADCAST_STORM BIT(1)
#define PORT_JUMBO_PACKET BIT(0)
#define REG_PORT_MAC_CTRL_1 0x0401
#define PORT_BACK_PRESSURE BIT(3)
#define PORT_PASS_ALL BIT(0)
#define PORT_MAX_FR_SIZE 0x404
#define FR_MIN_SIZE 1522
/* 8 - Classification and Policing */
#define REG_PORT_MRI_PRIO_CTRL 0x0801
#define PORT_HIGHEST_PRIO BIT(7)
#define PORT_OR_PRIO BIT(6)
#define PORT_MAC_PRIO_ENABLE BIT(4)
#define PORT_VLAN_PRIO_ENABLE BIT(3)
#define PORT_802_1P_PRIO_ENABLE BIT(2)
#define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
#define PORT_ACL_PRIO_ENABLE BIT(0)
#define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL
#define LAN937X_TAG_LEN 2
#endif
|
