1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
|
/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef MOD_HDCP_H_
#define MOD_HDCP_H_
#include "os_types.h"
#include "signal_types.h"
/* Forward Declarations */
struct mod_hdcp;
#define MAX_NUM_OF_DISPLAYS 6
#define MAX_NUM_OF_ATTEMPTS 4
#define MAX_NUM_OF_ERROR_TRACE 10
/* detailed return status */
enum mod_hdcp_status {
MOD_HDCP_STATUS_SUCCESS = 0,
MOD_HDCP_STATUS_FAILURE,
MOD_HDCP_STATUS_RESET_NEEDED,
MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND,
MOD_HDCP_STATUS_DISPLAY_NOT_FOUND,
MOD_HDCP_STATUS_INVALID_STATE,
MOD_HDCP_STATUS_NOT_IMPLEMENTED,
MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE,
MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE,
MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE,
MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE,
MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE,
MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE,
MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE,
MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER,
MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE,
MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING,
MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE,
MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY,
MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE,
MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION,
MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE,
MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE,
MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE,
MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE,
MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE,
MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED,
MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE,
MOD_HDCP_STATUS_HDCP1_INVALID_BKSV,
MOD_HDCP_STATUS_DDC_FAILURE, /* TODO: specific errors */
MOD_HDCP_STATUS_INVALID_OPERATION,
MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE,
MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE,
MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE,
MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE,
MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING,
MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING,
MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING,
MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE,
MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE,
MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE,
MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE,
MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING,
MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE,
MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE,
MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE,
MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY,
MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE,
MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION,
MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING,
MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE,
MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE,
MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST,
MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE,
MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE,
};
struct mod_hdcp_displayport {
uint8_t rev;
uint8_t assr_supported;
};
struct mod_hdcp_hdmi {
uint8_t reserved;
};
enum mod_hdcp_operation_mode {
MOD_HDCP_MODE_OFF,
MOD_HDCP_MODE_DEFAULT,
MOD_HDCP_MODE_DP,
MOD_HDCP_MODE_DP_MST
};
enum mod_hdcp_display_state {
MOD_HDCP_DISPLAY_INACTIVE = 0,
MOD_HDCP_DISPLAY_ACTIVE,
MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED,
MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED
};
struct mod_hdcp_ddc {
void *handle;
struct {
bool (*read_i2c)(void *handle,
uint32_t address,
uint8_t offset,
uint8_t *data,
uint32_t size);
bool (*write_i2c)(void *handle,
uint32_t address,
const uint8_t *data,
uint32_t size);
bool (*read_dpcd)(void *handle,
uint32_t address,
uint8_t *data,
uint32_t size);
bool (*write_dpcd)(void *handle,
uint32_t address,
const uint8_t *data,
uint32_t size);
} funcs;
};
struct mod_hdcp_psp {
void *handle;
void *funcs;
};
struct mod_hdcp_display_adjustment {
uint8_t disable : 1;
uint8_t reserved : 7;
};
struct mod_hdcp_link_adjustment_hdcp1 {
uint8_t disable : 1;
uint8_t postpone_encryption : 1;
uint8_t reserved : 6;
};
struct mod_hdcp_link_adjustment_hdcp2 {
uint8_t disable : 1;
uint8_t disable_type1 : 1;
uint8_t force_no_stored_km : 1;
uint8_t increase_h_prime_timeout: 1;
uint8_t reserved : 4;
};
struct mod_hdcp_link_adjustment {
uint8_t auth_delay;
struct mod_hdcp_link_adjustment_hdcp1 hdcp1;
struct mod_hdcp_link_adjustment_hdcp2 hdcp2;
};
struct mod_hdcp_error {
enum mod_hdcp_status status;
uint8_t state_id;
};
struct mod_hdcp_trace {
struct mod_hdcp_error errors[MAX_NUM_OF_ERROR_TRACE];
uint8_t error_count;
};
enum mod_hdcp_encryption_status {
MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF = 0,
MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON,
MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON,
MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON
};
/* per link events dm has to notify to hdcp module */
enum mod_hdcp_event {
MOD_HDCP_EVENT_CALLBACK = 0,
MOD_HDCP_EVENT_WATCHDOG_TIMEOUT,
MOD_HDCP_EVENT_CPIRQ
};
/* output flags from module requesting timer operations */
struct mod_hdcp_output {
uint8_t callback_needed;
uint8_t callback_stop;
uint8_t watchdog_timer_needed;
uint8_t watchdog_timer_stop;
uint16_t callback_delay;
uint16_t watchdog_timer_delay;
};
/* used to represent per display info */
struct mod_hdcp_display {
enum mod_hdcp_display_state state;
uint8_t index;
uint8_t controller;
uint8_t dig_fe;
union {
uint8_t vc_id;
};
struct mod_hdcp_display_adjustment adjust;
};
/* used to represent per link info */
/* in case a link has multiple displays, they share the same link info */
struct mod_hdcp_link {
enum mod_hdcp_operation_mode mode;
uint8_t dig_be;
uint8_t ddc_line;
union {
struct mod_hdcp_displayport dp;
struct mod_hdcp_hdmi hdmi;
};
struct mod_hdcp_link_adjustment adjust;
};
/* a query structure for a display's hdcp information */
struct mod_hdcp_display_query {
const struct mod_hdcp_display *display;
const struct mod_hdcp_link *link;
const struct mod_hdcp_trace *trace;
enum mod_hdcp_encryption_status encryption_status;
};
/* contains values per on external display configuration change */
struct mod_hdcp_config {
struct mod_hdcp_psp psp;
struct mod_hdcp_ddc ddc;
uint8_t index;
};
struct mod_hdcp;
/* dm allocates memory of mod_hdcp per dc_link on dm init based on memory size*/
size_t mod_hdcp_get_memory_size(void);
/* called per link on link creation */
enum mod_hdcp_status mod_hdcp_setup(struct mod_hdcp *hdcp,
struct mod_hdcp_config *config);
/* called per link on link destroy */
enum mod_hdcp_status mod_hdcp_teardown(struct mod_hdcp *hdcp);
/* called per display on cp_desired set to true */
enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp *hdcp,
struct mod_hdcp_link *link, struct mod_hdcp_display *display,
struct mod_hdcp_output *output);
/* called per display on cp_desired set to false */
enum mod_hdcp_status mod_hdcp_remove_display(struct mod_hdcp *hdcp,
uint8_t index, struct mod_hdcp_output *output);
/* called to query hdcp information on a specific index */
enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
uint8_t index, struct mod_hdcp_display_query *query);
/* called per link on connectivity change */
enum mod_hdcp_status mod_hdcp_reset_connection(struct mod_hdcp *hdcp,
struct mod_hdcp_output *output);
/* called per link on events (i.e. callback, watchdog, CP_IRQ) */
enum mod_hdcp_status mod_hdcp_process_event(struct mod_hdcp *hdcp,
enum mod_hdcp_event event, struct mod_hdcp_output *output);
/* called to convert enum mod_hdcp_status to c string */
char *mod_hdcp_status_to_str(int32_t status);
/* called to convert state id to c string */
char *mod_hdcp_state_id_to_str(int32_t id);
/* called to convert signal type to operation mode */
enum mod_hdcp_operation_mode mod_hdcp_signal_type_to_operation_mode(
enum signal_type signal);
#endif /* MOD_HDCP_H_ */
|