blob: 4c0d576e8c21883e4a87f9000d8d867f5b81c466 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright(c) 2025 Intel Corporation */
#ifndef ADF_GEN6_PM_H
#define ADF_GEN6_PM_H
#include <linux/bits.h>
#include <linux/time.h>
struct adf_accel_dev;
/* Power management */
#define ADF_GEN6_PM_POLL_DELAY_US 20
#define ADF_GEN6_PM_POLL_TIMEOUT_US USEC_PER_SEC
#define ADF_GEN6_PM_STATUS 0x50A00C
#define ADF_GEN6_PM_INTERRUPT 0x50A028
/* Power management source in ERRSOU2 and ERRMSK2 */
#define ADF_GEN6_PM_SOU BIT(18)
/* cpm_pm_interrupt bitfields */
#define ADF_GEN6_PM_DRV_ACTIVE BIT(20)
#define ADF_GEN6_PM_DEFAULT_IDLE_FILTER 0x6
/* cpm_pm_status bitfields */
#define ADF_GEN6_PM_INIT_STATE BIT(21)
#define ADF_GEN6_PM_CPM_PM_STATE_MASK GENMASK(22, 20)
/* fusectl0 bitfields */
#define ADF_GEN6_PM_ENABLE_PM_MASK BIT(21)
#define ADF_GEN6_PM_ENABLE_PM_IDLE_MASK BIT(22)
#define ADF_GEN6_PM_ENABLE_DEEP_PM_IDLE_MASK BIT(23)
/* cpm_pm_fw_init bitfields */
#define ADF_GEN6_PM_IDLE_FILTER_MASK GENMASK(5, 3)
#define ADF_GEN6_PM_IDLE_ENABLE_MASK BIT(2)
/* ssm_pm_enable bitfield */
#define ADF_GEN6_PM_SSM_PM_ENABLE_MASK BIT(0)
/* ssm_pm_domain_status bitfield */
#define ADF_GEN6_PM_DOMAIN_POWERED_UP_MASK BIT(0)
#ifdef CONFIG_DEBUG_FS
void adf_gen6_init_dev_pm_data(struct adf_accel_dev *accel_dev);
#else
static inline void adf_gen6_init_dev_pm_data(struct adf_accel_dev *accel_dev)
{
}
#endif /* CONFIG_DEBUG_FS */
#endif /* ADF_GEN6_PM_H */
|
