blob: 2afcbd39e41e9a709ce4f7cb9c98513c1db9d378 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
config SUNXI_CCU
bool "Clock support for Allwinner SoCs"
default ARCH_SUNXI
if SUNXI_CCU
# Base clock types
config SUNXI_CCU_DIV
bool
select SUNXI_CCU_MUX
config SUNXI_CCU_FRAC
bool
config SUNXI_CCU_GATE
bool
config SUNXI_CCU_MUX
bool
config SUNXI_CCU_PHASE
bool
# Multi-factor clocks
config SUNXI_CCU_NK
bool
select SUNXI_CCU_GATE
config SUNXI_CCU_NKM
bool
select RATIONAL
select SUNXI_CCU_GATE
config SUNXI_CCU_NKMP
bool
select RATIONAL
select SUNXI_CCU_GATE
config SUNXI_CCU_NM
bool
select RATIONAL
select SUNXI_CCU_FRAC
select SUNXI_CCU_GATE
config SUNXI_CCU_MP
bool
select SUNXI_CCU_GATE
select SUNXI_CCU_MUX
# SoC Drivers
config SUN8I_H3_CCU
bool "Support for the Allwinner H3 CCU"
select SUNXI_CCU_DIV
select SUNXI_CCU_NK
select SUNXI_CCU_NKM
select SUNXI_CCU_NKMP
select SUNXI_CCU_NM
select SUNXI_CCU_MP
select SUNXI_CCU_PHASE
default MACH_SUN8I
endif
|
