blob: 80e7d8ab9f1bb81ad4a70fb8805a45bb170ff01f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MX35 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*/
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include "hardware.h"
#include "iim.h"
static int mx35_cpu_rev = -1;
static int mx35_read_cpu_rev(void)
{
void __iomem *iim_base;
struct device_node *np;
u32 rev;
np = of_find_compatible_node(NULL, NULL, "fsl,imx35-iim");
iim_base = of_iomap(np, 0);
BUG_ON(!iim_base);
rev = imx_readl(iim_base + MXC_IIMSREV);
switch (rev) {
case 0x00:
return IMX_CHIP_REVISION_1_0;
case 0x10:
return IMX_CHIP_REVISION_2_0;
case 0x11:
return IMX_CHIP_REVISION_2_1;
default:
return IMX_CHIP_REVISION_UNKNOWN;
}
}
int mx35_revision(void)
{
if (mx35_cpu_rev == -1)
mx35_cpu_rev = mx35_read_cpu_rev();
return mx35_cpu_rev;
}
EXPORT_SYMBOL(mx35_revision);
|
