1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCIe RC controller on Intel Gateway SoCs
maintainers:
- Rahul Tanwar <rtanwar@maxlinear.com>
select:
properties:
compatible:
contains:
const: intel,lgm-pcie
required:
- compatible
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
items:
- const: intel,lgm-pcie
- const: snps,dw-pcie
reg:
items:
- description: Controller control and status registers.
- description: PCIe configuration registers.
- description: Controller application registers.
reg-names:
items:
- const: dbi
- const: config
- const: app
ranges:
maxItems: 1
resets:
maxItems: 1
clocks:
maxItems: 1
phys:
maxItems: 1
phy-names:
const: pcie
reset-gpios:
maxItems: 1
num-lanes:
maximum: 2
max-link-speed:
enum: [1, 2, 3, 4]
default: 1
reset-assert-ms:
description: |
Delay after asserting reset to the PCIe device.
maximum: 500
default: 100
required:
- compatible
- reg
- reg-names
- ranges
- resets
- clocks
- phys
- phy-names
- reset-gpios
- '#interrupt-cells'
- interrupt-map
- interrupt-map-mask
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
pcie10: pcie@d0e00000 {
compatible = "intel,lgm-pcie", "snps,dw-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0xd0e00000 0x1000>,
<0xd2000000 0x800000>,
<0xd0a41000 0x1000>;
reg-names = "dbi", "config", "app";
linux,pci-domain = <0>;
max-link-speed = <4>;
bus-range = <0x00 0x08>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &ioapic1 27 1>,
<0 0 0 2 &ioapic1 28 1>,
<0 0 0 3 &ioapic1 29 1>,
<0 0 0 4 &ioapic1 30 1>;
ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
resets = <&rcu0 0x50 0>;
clocks = <&cgu0 120>;
phys = <&cb0phy0>;
phy-names = "pcie";
reset-assert-ms = <500>;
reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
num-lanes = <2>;
};
|
