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|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip internal OTP (One Time Programmable) memory
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,px30-otp
- rockchip,rk3308-otp
- rockchip,rk3588-otp
reg:
maxItems: 1
clocks:
minItems: 3
maxItems: 4
clock-names:
minItems: 3
items:
- const: otp
- const: apb_pclk
- const: phy
- const: arb
resets:
minItems: 1
maxItems: 3
reset-names:
minItems: 1
maxItems: 3
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
allOf:
- $ref: nvmem.yaml#
- if:
properties:
compatible:
contains:
enum:
- rockchip,px30-otp
- rockchip,rk3308-otp
then:
properties:
clocks:
maxItems: 3
resets:
maxItems: 1
reset-names:
items:
- const: phy
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3588-otp
then:
properties:
clocks:
minItems: 4
resets:
minItems: 3
reset-names:
items:
- const: otp
- const: apb
- const: arb
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/px30-cru.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
otp: efuse@ff290000 {
compatible = "rockchip,px30-otp";
reg = <0x0 0xff290000 0x0 0x4000>;
clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
<&cru PCLK_OTP_PHY>;
clock-names = "otp", "apb_pclk", "phy";
resets = <&cru SRST_OTP_PHY>;
reset-names = "phy";
#address-cells = <1>;
#size-cells = <1>;
cpu_id: id@7 {
reg = <0x07 0x10>;
};
cpu_leakage: cpu-leakage@17 {
reg = <0x17 0x1>;
};
performance: performance@1e {
reg = <0x1e 0x1>;
bits = <4 3>;
};
};
};
|
