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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/cdns,macb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence MACB/GEM Ethernet controller
maintainers:
- Nicolas Ferre <nicolas.ferre@microchip.com>
- Claudiu Beznea <claudiu.beznea@microchip.com>
properties:
compatible:
oneOf:
- items:
- enum:
- cdns,at91rm9200-emac # Atmel at91rm9200 SoC
- const: cdns,emac # Generic
- items:
- enum:
- cdns,zynq-gem # Xilinx Zynq-7xxx SoC
- cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
- const: cdns,gem # Generic
deprecated: true
- items:
- enum:
- xlnx,versal-gem # Xilinx Versal
- xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
- xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
- const: cdns,gem # Generic
- items:
- enum:
- cdns,at91sam9260-macb # Atmel at91sam9 SoCs
- cdns,sam9x60-macb # Microchip sam9x60 SoC
- microchip,mpfs-macb # Microchip PolarFire SoC
- const: cdns,macb # Generic
- items:
- enum:
- atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs
- enum:
- cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
- const: cdns,macb # Generic
- enum:
- atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
- atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
- atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs
- atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs
- cdns,np4-macb # NP4 SoC devices
- microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
- microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
- sifive,fu540-c000-gem # SiFive FU540-C000 SoC
- cdns,emac # Generic
- cdns,gem # Generic
- cdns,macb # Generic
reg:
minItems: 1
items:
- description: Basic register set
- description: GEMGXL Management block registers on SiFive FU540-C000 SoC
interrupts:
minItems: 1
maxItems: 8
description: One interrupt per available hardware queue
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
items:
- enum: [ ether_clk, hclk, pclk ]
- enum: [ hclk, pclk ]
- const: tx_clk
- enum: [ rx_clk, tsu_clk ]
- const: tsu_clk
local-mac-address: true
phy-mode: true
phy-handle: true
phys:
maxItems: 1
resets:
maxItems: 1
description:
Recommended with ZynqMP, specify reset control for this
controller instance with zynqmp-reset driver.
reset-names:
maxItems: 1
fixed-link: true
iommus:
maxItems: 1
power-domains:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
mdio:
type: object
description:
Node containing PHY children. If this node is not present, then PHYs will
be direct children.
patternProperties:
"^ethernet-phy@[0-9a-f]$":
type: object
$ref: ethernet-phy.yaml#
properties:
reset-gpios: true
magic-packet:
type: boolean
description:
Indicates that the hardware supports waking up via magic packet.
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- phy-mode
allOf:
- $ref: ethernet-controller.yaml#
- if:
not:
properties:
compatible:
contains:
const: sifive,fu540-c000-gem
then:
properties:
reg:
maxItems: 1
unevaluatedProperties: false
examples:
- |
macb0: ethernet@fffc4000 {
compatible = "cdns,macb";
reg = <0xfffc4000 0x4000>;
interrupts = <21>;
phy-mode = "rmii";
local-mac-address = [3a 0e 03 04 05 06];
clock-names = "pclk", "hclk", "tx_clk";
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
#address-cells = <1>;
#size-cells = <0>;
ethernet-phy@1 {
reg = <0x1>;
reset-gpios = <&pioE 6 1>;
};
};
- |
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
#include <dt-bindings/phy/phy.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
gem1: ethernet@ff0c0000 {
compatible = "xlnx,zynqmp-gem", "cdns,gem";
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
reset-names = "gem1_rst";
phy-mode = "sgmii";
phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
|
