1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek JPEG Decoder
maintainers:
- kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
description:
MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs
properties:
compatible:
const: mediatek,mt8195-jpgdec
power-domains:
maxItems: 1
iommus:
maxItems: 6
description:
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
# Required child node:
patternProperties:
"^jpgdec@[0-9a-f]+$":
type: object
description:
The jpeg decoder hardware device node which should be added as subnodes to
the main jpeg node.
properties:
compatible:
const: mediatek,mt8195-jpgdec-hw
reg:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description:
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: jpgdec
power-domains:
maxItems: 1
required:
- compatible
- reg
- iommus
- interrupts
- clocks
- clock-names
- power-domains
additionalProperties: false
required:
- compatible
- power-domains
- iommus
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
jpgdec-master {
compatible = "mediatek,mt8195-jpgdec";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
jpgdec@1a040000 {
compatible = "mediatek,mt8195-jpgdec-hw";
reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGDEC>;
clock-names = "jpgdec";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
};
jpgdec@1a050000 {
compatible = "mediatek,mt8195-jpgdec-hw";
reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
clock-names = "jpgdec";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
};
jpgdec@1b040000 {
compatible = "mediatek,mt8195-jpgdec-hw";
reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
clock-names = "jpgdec";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
};
};
};
|