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path: root/drivers/irqchip
AgeCommit message (Expand)AuthorFilesLines
7 daysirqchip/mchp-eic: Fix error code in mchp_eic_domain_alloc()Dan Carpenter1-1/+1
7 daysirqchip/qcom-irq-combiner: Fix section mismatchJohan Hovold1-1/+1
7 daysirqchip/starfive-jh8100: Fix section mismatchJohan Hovold1-2/+1
7 daysirqchip/renesas-rzg2l: Fix section mismatchJohan Hovold1-4/+2
7 daysirqchip/imx-mu-msi: Fix section mismatchJohan Hovold1-9/+5
7 daysirqchip/irq-brcmstb-l2: Fix section mismatchJohan Hovold1-8/+4
7 daysirqchip/irq-bcm7120-l2: Fix section mismatchJohan Hovold1-11/+6
7 daysirqchip/irq-bcm7038-l1: Fix section mismatchJohan Hovold1-5/+3
2025-11-24irqchip/riscv-intc: Add missing free() callback in riscv_intc_domain_opsNick Hu1-1/+2
2025-11-13irqchip/loongson-pch-lpc: Use legacy domain for PCH-LPC IRQ controllerMing Wang1-2/+7
2025-11-13irqchip/gic-v2m: Handle Multiple MSI base IRQ AlignmentChristian Bruel1-4/+9
2025-11-13irqchip/sifive-plic: Respect mask state when setting affinityInochi Amaoto1-2/+4
2025-10-19irqchip/sifive-plic: Avoid interrupt ID 0 handling during suspend/resumeLucas Zampieri1-2/+4
2025-10-19irqchip/sifive-plic: Make use of __assign_bit()Hongbo Li1-5/+4
2025-08-15irqchip: Build IMX_MU_MSI only on ARMArnd Bergmann1-0/+1
2025-07-17irqchip/irq-msi-lib: Select CONFIG_GENERIC_MSI_IRQNam Cao1-0/+1
2025-05-29irqchip/riscv-imsic: Start local sync timer on correct CPUAndrew Bresticker1-5/+5
2025-05-29irqchip/riscv-aplic: Add support for hart indexesVladimir Kondratiev1-3/+21
2025-05-29irqchip/riscv-imsic: Set irq_set_affinity() for IMSIC baseAndrew Jones1-7/+9
2025-05-29irqchip/riscv-imsic: Separate next and previous pointers in IMSIC vectorAnup Patel3-33/+78
2025-05-09irqchip/qcom-mpm: Prevent crash when trying to handle non-wake GPIOsStephan Gerhold1-0/+3
2025-05-02irqchip/gic-v2m: Prevent use after free of gicv2m_get_fwnode()Suzuki K Poulose1-1/+1
2025-02-27irqchip/gic-v3: Fix rk3399 workaround when secure interrupts are enabledMarc Zyngier1-13/+40
2025-02-27irqchip/jcore-aic, clocksource/drivers/jcore: Fix jcore-pit interrupt requestArtur Rojek1-1/+1
2025-02-17irqchip/apple-aic: Only handle PMC interrupt as FIQ when configured soNick Chan1-1/+2
2025-02-17irqchip/irq-mvebu-icu: Fix access to msi_data from irq_domain::host_dataStefan Eichenberger1-1/+2
2025-02-17irqchip/lan966x-oic: Make CONFIG_LAN966X_OIC depend on CONFIG_MCHP_LAN966X_PCIGeert Uytterhoeven1-0/+1
2025-02-01irqchip/sunxi-nmi: Add missing SKIP_WAKE flagPhilippe Simons1-1/+2
2025-01-23irqchip/gic-v3-its: Don't enable interrupts in its_irq_set_vcpu_affinity()Tomas Krcka1-1/+1
2025-01-23irqchip/gic-v3: Handle CPU_PM_ENTER_FAILED correctlyYogesh Lal1-1/+1
2025-01-23irqchip: Plug a OF node reference leak in platform_irqchip_probe()Joe Hattori1-3/+1
2025-01-09irqchip/gic: Correct declaration of *percpu_base pointer in union gic_baseUros Bizjak1-1/+1
2024-12-27irqchip/gic-v3: Work around insecure GIC integrationsMarc Zyngier1-1/+16
2024-12-14irqchip/gicv3-its: Add workaround for hip09 ITS erratum 162100801Zhou Wang1-11/+39
2024-12-14irqchip/stm32mp-exti: CONFIG_STM32MP_EXTI should not default to y when compil...Geert Uytterhoeven1-1/+1
2024-12-05irqchip/irq-mvebu-sei: Move misplaced select() callback to SEI CP domainRussell King (Oracle)1-1/+1
2024-12-05irqchip/riscv-aplic: Prevent crash when MSI domain is missingSamuel Holland2-1/+5
2024-11-07irqchip/gic-v3: Force propagation of the active state with a read-backMarc Zyngier1-0/+7
2024-10-27irqchip/gic-v4: Correctly deal with set_affinity on lazily-mapped VPEsMarc Zyngier1-2/+12
2024-10-16irqchip/renesas-rzg2l: Fix missing put_deviceFabrizio Castro1-2/+14
2024-10-16irqchip/riscv-intc: Fix SMP=n boot with ACPISunil V L1-1/+18
2024-10-08irqchip/sifive-plic: Unmask interrupt in plic_irq_enable()Nam Cao1-10/+11
2024-10-08irqchip/gic-v4: Don't allow a VMOVP on a dying VPEMarc Zyngier1-6/+12
2024-10-02irqchip/sifive-plic: Return error code on failureCharlie Jenkins1-2/+6
2024-10-02irqchip/riscv-imsic: Fix output text of base addressAndrew Jones1-1/+1
2024-10-02irqchip/ocelot: Comment sticky register clearing codeSergey Matsievskiy1-0/+6
2024-10-02irqchip/ocelot: Fix trigger register addressSergey Matsievskiy1-2/+2
2024-10-02irqchip: Remove obsolete config ARM_GIC_V3_ITS_PCILukas Bulwahn1-7/+0
2024-09-17Merge tag 'irq-core-2024-09-16' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds25-520/+1014
2024-09-04irqchip/apple-aic: Only access system registers on SoCs which provide themKonrad Dybcio1-13/+13
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