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path: root/drivers/irqchip
AgeCommit message (Expand)AuthorFilesLines
8 daysirqchip/mchp-eic: Fix error code in mchp_eic_domain_alloc()Dan Carpenter1-1/+1
8 daysirqchip/qcom-irq-combiner: Fix section mismatchJohan Hovold1-1/+1
8 daysirqchip/imx-mu-msi: Fix section mismatchJohan Hovold1-9/+5
8 daysirqchip/irq-brcmstb-l2: Fix section mismatchJohan Hovold1-8/+4
8 daysirqchip/irq-bcm7120-l2: Fix section mismatchJohan Hovold1-11/+6
8 daysirqchip/irq-bcm7038-l1: Fix section mismatchJohan Hovold1-5/+3
2025-11-24irqchip/riscv-intc: Add missing free() callback in riscv_intc_domain_opsNick Hu1-1/+2
2025-11-24irqchip/loongson-pch-lpc: Use legacy domain for PCH-LPC IRQ controllerMing Wang1-2/+7
2025-11-24irqchip/gic-v2m: Handle Multiple MSI base IRQ AlignmentChristian Bruel1-4/+9
2025-11-24irqchip/sifive-plic: Respect mask state when setting affinityInochi Amaoto1-2/+4
2025-10-19irqchip/sifive-plic: Avoid interrupt ID 0 handling during suspend/resumeLucas Zampieri1-2/+4
2025-10-19irqchip/sifive-plic: Make use of __assign_bit()Hongbo Li1-5/+4
2025-10-02minmax: don't use max() in situations that want a C constant expressionLinus Torvalds1-1/+1
2025-08-15irqchip: Build IMX_MU_MSI only on ARMArnd Bergmann1-0/+1
2025-05-09irqchip/qcom-mpm: Prevent crash when trying to handle non-wake GPIOsStephan Gerhold1-0/+3
2025-05-02irqchip/gic-v2m: Prevent use after free of gicv2m_get_fwnode()Suzuki K Poulose1-1/+1
2025-02-17irqchip/apple-aic: Only handle PMC interrupt as FIQ when configured soNick Chan1-1/+2
2025-02-08of: remove internal arguments from of_property_for_each_u32()Luca Ceresoli2-6/+2
2025-02-01irqchip/sunxi-nmi: Add missing SKIP_WAKE flagPhilippe Simons1-1/+2
2025-01-23irqchip/gic-v3-its: Don't enable interrupts in its_irq_set_vcpu_affinity()Tomas Krcka1-1/+1
2025-01-23irqchip/gic-v3: Handle CPU_PM_ENTER_FAILED correctlyYogesh Lal1-1/+1
2025-01-23irqchip: Plug a OF node reference leak in platform_irqchip_probe()Joe Hattori1-3/+1
2025-01-09irqchip/gic: Correct declaration of *percpu_base pointer in union gic_baseUros Bizjak1-1/+1
2024-11-17irqchip/ocelot: Fix trigger register addressSergey Matsievskiy1-2/+2
2024-11-14irqchip/gic-v3: Force propagation of the active state with a read-backMarc Zyngier1-0/+7
2024-11-01irqchip/renesas-rzg2l: Fix missing put_deviceFabrizio Castro1-2/+14
2024-11-01irqchip/renesas-rzg2l: Add support for suspend to RAMClaudiu Beznea1-11/+57
2024-11-01irqchip/renesas-rzg2l: Document structure membersClaudiu Beznea1-0/+6
2024-11-01irqchip/renesas-rzg2l: Align struct member names to tabsClaudiu Beznea1-3/+3
2024-10-22irqchip/sifive-plic: Unmask interrupt in plic_irq_enable()Nam Cao1-10/+11
2024-10-22irqchip/gic-v4: Don't allow a VMOVP on a dying VPEMarc Zyngier1-6/+12
2024-10-22irqchip/gic-v3-its: Fix VSYNC referencing an unmapped VPE on GIC v4.1Nianyao Tang1-1/+7
2024-09-12irqchip/armada-370-xp: Do not allow mapping IRQ 0 and 1Pali Rohár1-0/+4
2024-09-12irqchip/gic-v2m: Fix refcount leak in gicv2m_of_init()Ma Ke1-3/+3
2024-08-29irqchip/gic-v3-its: Remove BUG_ON in its_vpe_irq_domain_allocGuanrui Huang1-2/+0
2024-08-29irqchip/renesas-rzg2l: Do not set TIEN and TINT source at the same timeBiju Das1-3/+2
2024-08-14irqchip/xilinx: Fix shift out of boundsRadhey Shyam Pandey1-1/+1
2024-08-14irqchip/loongarch-cpu: Fix return value of lpic_gsi_to_irq()Huacai Chen1-2/+4
2024-08-14irqchip/meson-gpio: Convert meson_gpio_irq_controller::lock to 'raw_spinlock_t'Arseniy Krasnov1-7/+7
2024-08-14irqchip/mbigen: Fix mbigen node address layoutYipeng Zou1-4/+16
2024-08-03irqchip/imx-irqsteer: Handle runtime power management correctlyShenwei Wang1-3/+21
2024-07-05irqchip/loongson-liointc: Set different ISRs for different coresHuacai Chen1-2/+2
2024-07-05irqchip/loongson-eiointc: Use early_cpu_to_node() instead of cpu_to_node()Huacai Chen1-2/+3
2024-07-05irqchip/loongson: Select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP for IRQ_LOONGA...Tiezhu Yang1-1/+1
2024-06-21irqchip/gic-v3-its: Fix potential race condition in its_vlpi_prop_update()Hagar Hemdan1-32/+12
2024-06-21irqchip/riscv-intc: Prevent memory leak when riscv_intc_init_common() failsSunil V L1-2/+7
2024-06-21irqchip/riscv-intc: Introduce Andes hart-level interrupt controllerYu Chien Peter Lin1-7/+51
2024-06-21irqchip/riscv-intc: Allow large non-standard interrupt numberYu Chien Peter Lin1-7/+19
2024-06-12irqchip/loongson-pch-msi: Fix off-by-one on allocation error pathZenghui Yu1-1/+1
2024-06-12irqchip/alpine-msi: Fix off-by-one in allocation error pathZenghui Yu1-1/+1
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