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path: root/drivers/iommu/intel/cache.c
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6 daysiommu/vt-d: Create unique domain ops for each stageJason Gunthorpe1-2/+3
2025-08-15iommu/vt-d: Fix missing PASID in dev TLB flush with cache_tag_flush_allEthan Milon1-17/+1
2025-07-04iommu/vt-d: Assign devtlb cache tag on ATS enablementLu Baolu1-3/+2
2025-01-07iommu/vt-d: Link cache tags of same iommu unit togetherZhenzhong Duan1-1/+10
2024-12-13iommu/vt-d: Fix qi_batch NULL pointer with nested parent domainYi Liu1-7/+27
2024-09-02iommu/vt-d: Introduce batched cache invalidationTina Zhang1-15/+107
2024-09-02iommu/vt-d: Add qi_batch for dmar_domainLu Baolu1-0/+7
2024-09-02iommu/vt-d: Refactor IOTLB and Dev-IOTLB flush for batchingTina Zhang1-64/+78
2024-07-10iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()Lu Baolu1-0/+1
2024-07-10iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTHLu Baolu1-1/+1
2024-04-26iommu/vt-d: Add trace events for cache tag interfaceLu Baolu1-0/+10
2024-04-26iommu/vt-d: Add cache tag invalidation helpersLu Baolu1-0/+195
2024-04-26iommu/vt-d: Add cache tag assignment interfaceLu Baolu1-0/+214