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path: root/drivers/gpu/drm/msm/dsi/phy
AgeCommit message (Expand)AuthorFilesLines
2025-12-07drm/msm/dsi/phy_7nm: Fix missing initial VCO rateKrzysztof Kozlowski1-0/+6
2025-12-07drm/msm/dsi/phy: Toggle back buffer resync after preparing PLLKrzysztof Kozlowski1-0/+4
2025-06-27drm/msm/dsi/dsi_phy_10nm: Fix missing initial VCO rateKrzysztof Kozlowski1-0/+7
2024-02-23drm/msm/dsi: Enable runtime PMKonrad Dybcio1-0/+4
2024-01-26drm/msm/dsi: Use pm_runtime_resume_and_get to prevent refcnt leaksKonrad Dybcio1-1/+3
2023-07-23drm/msm/dsi: don't allow enabling 14nm VCO with unprogrammed rateDmitry Baryshkov1-0/+3
2022-09-08drm/msm/dsi: fix the inconsistent indentingsunliming1-1/+1
2022-06-09drm/msm/dsi: fix address for second DSI PHY on SDM660Dmitry Baryshkov1-1/+1
2022-04-08drm/msm/dsi/phy: fix 7nm v4.0 settings for C-PHY modeDmitry Baryshkov1-8/+14
2022-04-08drm/msm/dsi: Use "ref" fw clock instead of global name for VCO parentMarijn Suijten5-5/+15
2022-02-01drm/msm/dsi: invalid parameter check in msm_dsi_phy_enableJosé Expósito1-1/+3
2021-10-12drm/msm/dsi: dsi_phy_14nm: Take ready-bit into account in poll_for_readyMarijn Suijten1-15/+15
2021-10-12drm/msm/dsi/phy: fix clock names in 28nm_8960 phyDmitry Baryshkov1-2/+2
2021-08-11drm/msm/dsi: add continuous clock support for 7nm PHYDmitry Baryshkov3-0/+27
2021-08-07drm/msm/dsi: Fix DSI and DSI PHY regulator config from SDM660Konrad Dybcio1-1/+1
2021-08-07drm/msm/dsi: rename dual DSI to bonded DSIDmitry Baryshkov3-5/+5
2021-08-07drm/msm/dsi: Add PHY configuration for SC7280Rajeev Nandan3-0/+29
2021-08-07drm/msm/dsi: drop msm_dsi_phy_get_shared_timingsDmitry Baryshkov1-8/+5
2021-08-07drm/msm/dsi: phy: use of_device_get_match_dataDmitry Baryshkov1-6/+4
2021-08-07drm/msm/dsi: support CPHY mode for 7nm pll/phyJonathan Marek3-43/+154
2021-06-23drm/msm: Generated register updateRob Clark6-0/+6
2021-06-23drm/msm/dsi: fix 32-bit clang warningArnd Bergmann1-1/+5
2021-06-23Merge branch 'msm-fixes-v5.13-rc6' into msm-next-redoRob Clark2-0/+2
2021-06-23drm/msm/dsi: add DSI PHY registers to snapshot dataDmitry Baryshkov2-4/+31
2021-06-10drm/msm/dsi: Stash away calculated vco frequency on recalcStephen Boyd2-0/+2
2021-04-27drm/msm/dsi: fix msm_dsi_phy_get_clk_provider return codeDmitry Baryshkov1-1/+1
2021-04-27drm/msm/dsi: dsi_phy_28nm_8960: fix uninitialized variable accessDmitry Baryshkov1-0/+4
2021-04-07drm/msm/dsi: stop passing src_pll_id to the phy_enable callDmitry Baryshkov8-12/+12
2021-04-07drm/msm/dsi: inline msm_dsi_phy_set_src_pllDmitry Baryshkov8-46/+21
2021-04-07drm/msm/dsi: remove temp data from global pll structureDmitry Baryshkov3-447/+220
2021-04-07drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instancesDmitry Baryshkov5-149/+119
2021-04-07drm/msm/dsi: move ioremaps to dsi_phy_driver_probeDmitry Baryshkov7-163/+108
2021-04-07drm/msm/dsi: drop PLL accessor functionsDmitry Baryshkov6-303/+283
2021-04-07drm/msm/dsi: drop msm_dsi_pll abstractionDmitry Baryshkov8-248/+221
2021-04-07drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phyDmitry Baryshkov7-83/+64
2021-04-07drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepareDmitry Baryshkov6-161/+171
2021-04-07drm/msm/dsi: simplify vco_delay handling in dsi_phy_28nm driverDmitry Baryshkov1-8/+4
2021-04-07drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm driversDmitry Baryshkov3-10/+0
2021-04-07drm/msm/dsi: make save/restore_state phy-level functionsDmitry Baryshkov6-49/+38
2021-04-07drm/msm/dsi: use devm_of_clk_add_hw_providerDmitry Baryshkov1-21/+1
2021-04-07drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocksDmitry Baryshkov9-245/+71
2021-04-07drm/msm/dsi: push provided clocks handling into a generic codeDmitry Baryshkov9-275/+70
2021-04-07drm/msm/dsi: remove msm_dsi_pll_set_usecaseDmitry Baryshkov5-20/+3
2021-04-07drm/msm/dsi: move min/max PLL rate to phy configDmitry Baryshkov8-23/+27
2021-04-07drm/msm/dsi: drop global msm_dsi_phy_type enumarationDmitry Baryshkov7-33/+25
2021-04-07drm/msm/dsi: move all PLL callbacks into PHY config structDmitry Baryshkov9-204/+191
2021-04-07drm/msm/dsi: drop multiple pll enable_seq supportDmitry Baryshkov5-56/+42
2021-04-07drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* codeDmitry Baryshkov7-0/+4339
2021-04-07drm/msm/dsi: replace PHY's init callback with configurable dataDmitry Baryshkov8-82/+31
2021-01-31drm/msm/dsi: Correct io_start for MSM8994 (20nm PHY)Konrad Dybcio1-1/+1
generated by cgit v1.2.3 (git 2.39.0) at 2026-01-25 19:02:09 +0300