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path: root/drivers/gpu/drm/i915
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2025-11-07Merge tag 'drm-misc-next-2025-11-05-1' of https://gitlab.freedesktop.org/drm/...Dave Airlie112-5/+180
2025-11-07Merge tag 'drm-intel-next-2025-11-04' of https://gitlab.freedesktop.org/drm/i...Dave Airlie158-2061/+7001
2025-11-04drm/i915/display: Extend i915_display_info with Type-C port detailsKhaled Almahallawy3-0/+24
2025-11-03drm/i915/display: Use display parent interface for i915 runtime pmJouni Högander1-20/+13
2025-11-03drm/i915/display: Runtime pm wrappers for display parent interfaceJouni Högander3-0/+81
2025-11-03drm/{i915, xe}/display: pass parent interface to display probeJani Nikula6-4/+26
2025-11-01drm/i915/ltphy: Modify the step that need to be skippedSuraj Kandpal1-30/+33
2025-11-01drm/i915/display: Aux Enable and Display powerwell timeoutsSuraj Kandpal1-2/+20
2025-11-01drm/i915/ltphy: Define LT PHY PLL state verify functionSuraj Kandpal4-1/+63
2025-11-01drm/i915/ltphy: Define function to readout LT Phy PLL stateSuraj Kandpal3-0/+50
2025-11-01drm/i915/ltphy: Define the LT Phy state compare functionSuraj Kandpal3-1/+68
2025-11-01drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequenceSuraj Kandpal2-0/+91
2025-11-01drm/i915/ltphy: Program LT Phy Voltage SwingSuraj Kandpal4-3/+88
2025-11-01drm/i915/ddi: Define LT Phy Swing tablesSuraj Kandpal2-1/+89
2025-11-01drm/i915/ltphy: Hook up LT Phy Enable & Disable sequencesSuraj Kandpal5-4/+37
2025-11-01drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequenceSuraj Kandpal3-0/+80
2025-11-01drm/i915/ltphy: Program the rest of the LT Phy Enable sequenceSuraj Kandpal3-2/+32
2025-11-01drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL stepsSuraj Kandpal2-0/+26
2025-11-01drm/i915/ltphy: Program the P2P Transaction flow for LT PhySuraj Kandpal5-5/+143
2025-11-01drm/i915/ltphy: Add function to calculate LT PHY port clockSuraj Kandpal3-0/+97
2025-11-01drm/i915/ltphy: Enable SSC during port clock programmingSuraj Kandpal1-0/+26
2025-11-01drm/i915/ltphy: Update the ltpll config table value for eDPSuraj Kandpal1-0/+4
2025-11-01drm/i915/ltphy: Program the VDR PLL registers for LT PHYSuraj Kandpal3-5/+45
2025-11-01drm/i915/ltphy: Add LT Phy Programming recipe tablesSuraj Kandpal4-1/+1036
2025-11-01drm/i915/ltphy: Read PHY_VDR_0_CONFIG registerSuraj Kandpal3-25/+123
2025-11-01drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequenceSuraj Kandpal3-3/+18
2025-11-01drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT PhySuraj Kandpal2-0/+38
2025-11-01drm/i915/cx0: Move the HDMI FRL function to intel_hdmiSuraj Kandpal3-18/+18
2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal7-1/+201
2025-11-01drm/i915/cx0: Change register bit naming for powerdown valuesSuraj Kandpal2-12/+12
2025-11-01drm/i915/ltphy: Add LT Phy related VDR and Pipe RegistersSuraj Kandpal1-0/+24
2025-10-31Merge tag 'drm-intel-gt-next-2025-10-29' of https://gitlab.freedesktop.org/dr...Simona Vetter4-7/+17
2025-10-31drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBCVinod Govindapillai4-17/+71
2025-10-31drm/i915/xe3p_lpd: extract pixel format valid routine for FP16 formatsVinod Govindapillai1-2/+17
2025-10-31drm/i915/xe3p_lpd: Add FBC support for FP16 formatsVinod Govindapillai1-0/+2
2025-10-31drm/i915/xe3p_lpd: Extend FBC support to UINT16 formatsSai Teja Pottumuttu1-5/+28
2025-10-31drm/i915/display: switch to intel_display_utils.hJani Nikula52-53/+65
2025-10-31drm/i915/display: add intel_display_vtd_active()Jani Nikula5-8/+23
2025-10-31drm/i915/display: add intel_display_run_as_guest()Jani Nikula4-2/+27
2025-10-31drm/i915/display: create intel_display_utils.hJani Nikula6-5/+14
2025-10-31drm/i915: split out separate files for jiffies timeout and wait helpersJani Nikula15-37/+73
2025-10-31drm/i915/dsi: debug log send packet sequence contentsJani Nikula1-3/+7
2025-10-31drm/i915/dsi: log send packet sequence errorsJani Nikula1-9/+13
2025-10-31drm/ttm: Replace multiple booleans with flags in device initTvrtko Ursulin1-1/+1
2025-10-31drm: include drm_print.h where neededJani Nikula112-4/+178
2025-10-30drm/i915/display: Expose sharpness strength propertyNemesa Garg1-0/+3
2025-10-30drm/i915/display: Enable/disable casfNemesa Garg1-0/+26
2025-10-30drm/i915/display: Set and get the casf configNemesa Garg2-6/+20
2025-10-30drm/i915/display: Configure the second scalerNemesa Garg4-7/+31
2025-10-30drm/i915/display: Add and compute scaler parameterNemesa Garg3-0/+54
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