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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
AgeCommit message (Expand)AuthorFilesLines
2018-11-29drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSIManasi Navare1-1/+3
2018-11-16drm/i195: spell out reverse on for_each macrosLucas De Marchi1-2/+2
2018-11-14drm/i915: Remove special case for power well 1/MISC_IO state verificationImre Deak1-8/+7
2018-11-14drm/i915: Use proper bool bitfield initializer in power well descsImre Deak1-11/+11
2018-11-14drm/i915/gen9_bc: Work around DMC bug zeroing power well requestsImre Deak1-1/+15
2018-11-14drm/i915/icl: Drop spurious register read from icl_dbuf_slices_updateMika Kuoppala1-3/+1
2018-11-08drm/i915/icl: Fix port B combo PHY context loss after DC transitionsImre Deak1-0/+8
2018-11-08drm/i915/cnl+: Move the combo PHY init/uninit code to a new fileImre Deak1-119/+8
2018-11-08drm/i915/icl: Fix combo PHY uninitImre Deak1-0/+4
2018-11-07drm/i915/icl: Fix power well 2 wrt. DC-off toggling orderImre Deak1-6/+6
2018-11-02drm/i915: Configure AUX_CH_CTL when enabling the AUX power domainImre Deak1-8/+42
2018-10-30drm/i915/icl: Enable DC9 as lowest possible state during screen-offAnimesh Manna1-11/+21
2018-10-23drm/i915: power_domains_init sort platforms newer-to-olderRodrigo Vivi1-9/+8
2018-10-16drm/i915/icl: apply Display WA #1178 to fix type C donglesLucas De Marchi1-0/+9
2018-09-27drm/i915: Unset reset pch handshake when PCH is not present in one placeJosé Roberto de Souza1-8/+20
2018-09-27drm/i915/runtime_pm: Share code to enable/disable PCH reset handshakeJosé Roberto de Souza1-13/+17
2018-09-19drm/i915/psr: Enable AUX-A IO power well on ICL for PSRDhinakaran Pandiyan1-0/+1
2018-09-14firmware/dmc/icl: load v1.07 on icelake.Anusha Srivatsa1-0/+3
2018-08-29drm/i915: Don't check power domains state in intel_power_domains_init_hw()Imre Deak1-5/+5
2018-08-24drm/i915: move lookup_power_well() upPaulo Zanoni1-25/+21
2018-08-24drm/i915: use for_each_power_well in lookup_power_well()Paulo Zanoni1-8/+3
2018-08-24drm/i915: WARN() if we can't lookup_power_well()Paulo Zanoni1-1/+9
2018-08-23drm/i915: Simplify condition to keep DMC active during S0ixImre Deak1-6/+7
2018-08-20drm/i915: Verify power domains after enabling themImre Deak1-6/+30
2018-08-16drm/i915: Refactor intel_display_set_init_power() logicImre Deak1-38/+95
2018-08-16drm/i915: Introduce intel_runtime_pm_disable to pair intel_runtime_pm_enableChris Wilson1-14/+29
2018-08-08drm/i915: Use existing power well IDs where possibleImre Deak1-7/+7
2018-08-08drm/i915: Make power well ID names more uniformImre Deak1-22/+23
2018-08-08drm/i915: Remove redundant power well IDsImre Deak1-60/+63
2018-08-08drm/i915/ddi: Use power well CTL IDX instead of IDImre Deak1-50/+252
2018-08-08drm/i915/vlv: Use power well CTL IDX instead of IDImre Deak1-14/+38
2018-08-08drm/i915: Constify power well descriptorsImre Deak1-89/+117
2018-08-08drm/i915/vlv: Remove redundant power well ID assertsImre Deak1-12/+0
2018-08-08drm/i915: Rename intel_power_domains_fini() to intel_power_domains_fini_hw()Imre Deak1-35/+34
2018-08-08drm/i915/icl: Fix power well anonymous union initializersImre Deak1-7/+15
2018-07-28drm/i915/icl: don't set CNL_DDI_CLOCK_REG_ACCESS_ON anymorePaulo Zanoni1-4/+0
2018-07-05drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva1-0/+1
2018-06-27drm/i915/icl: Add power well supportImre Deak1-7/+322
2018-06-26drm/i915/ddi: Get AUX power domain for DP main link tooImre Deak1-0/+1
2018-06-13drm/i915/icl: DP_AUX_E is valid on ICL+James Ausmus1-0/+2
2018-05-07drm/i915: Add documentation to gen9_set_dc_state()Imre Deak1-0/+23
2018-04-28drm/i915/icl: Enable 2nd DBuf slice only when neededMahesh Kumar1-14/+51
2018-04-28drm/i915/icl: track dbuf slice-2 statusMahesh Kumar1-0/+4
2018-04-20drm/i915: Remove skl dc6 enable/disable functionsDaniel Vetter1-8/+1
2018-04-20drm/i915: Enable display WA#1183 from its correct spotImre Deak1-6/+5
2018-02-27drm/i915/psr: New power domain for AUX IO.Dhinakaran Pandiyan1-0/+3
2018-02-19drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_useChris Wilson1-8/+7
2018-02-13drm/i915/icl: initialize MBus during display initMahesh Kumar1-1/+13
2018-02-13drm/i915/icl: Enable both DBuf slices during initMahesh Kumar1-2/+32
2018-02-13drm/i915/icl: implement the display init/uninit sequencesPaulo Zanoni1-2/+80
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