summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
AgeCommit message (Expand)AuthorFilesLines
2015-12-02drm/i915: Introduce a gmbus power domainVille Syrjälä1-30/+4
2015-11-07Merge tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/...Dave Airlie1-0/+18
2015-11-06drm/i915/skl: disable display side power well support for nowImre Deak1-0/+18
2015-10-20Merge tag 'drm-intel-next-2015-10-10' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-7/+54
2015-10-16Merge commit '06d1ee32a4d25356a710b49d5e95dbdd68bdf505' of git://git.kernel.o...Dave Airlie1-1/+2
2015-10-06drm/i915: Skip CHV PHY asserts until PHY has been fully resetVille Syrjälä1-1/+45
2015-09-30drm/i915: fixup runtime PM handling v2Jesse Barnes1-3/+0
2015-09-30drm/i915/skl: Block disable call for pw1 if dmc firmware is present.Animesh Manna1-3/+9
2015-09-28drm/i915/skl: Don't call intel_prepare_ddi when encoder list isn't yet initia...Rodrigo Vivi1-1/+2
2015-09-14drm/i915: make CSR firmware messages less verboseJesse Barnes1-18/+18
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter1-0/+2
2015-09-01drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä1-17/+109
2015-09-01drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä1-0/+54
2015-08-31drm/i915/skl: Adding DDI_E power well domainXiong Zhang1-0/+2
2015-08-26drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä1-0/+9
2015-08-26drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä1-1/+2
2015-08-26drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä1-0/+29
2015-08-26drm/i915: Implement PHY lane power gating for CHVVille Syrjälä1-9/+114
2015-08-26drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enableVille Syrjälä1-21/+24
2015-08-26drm/i915: Add locking around chv_phy_control_init()Ville Syrjälä1-0/+2
2015-08-05drm/i915: Extract a intel_power_well_disable() functionDamien Lespiau1-5/+10
2015-08-05drm/i915: Extract a intel_power_well_enable() functionDamien Lespiau1-5/+10
2015-07-13drm/i915: Refactor VLV display power well init/deinitVille Syrjälä1-29/+23
2015-07-13drm/i915: Simplify CHV pipe A power well codeVille Syrjälä1-27/+20
2015-07-13drm/i915: Apply OCD to VLV/CHV DPLL definesVille Syrjälä1-4/+4
2015-07-13drm/i915: Keep GMCH DPLL VGA mode always disabledVille Syrjälä1-4/+4
2015-05-28drm/i915: Throw out WIP CHV power well definitionsVille Syrjälä1-94/+4
2015-05-28drm/i915: Use the default 600ns LDO programming sequence delayVille Syrjälä1-0/+2
2015-05-20drm/i915: Fix typo in intel_runtime_pm.cMasanari Iida1-2/+2
2015-05-08Revert "drm/i915: Hack to tie both common lanes together on chv"Ville Syrjälä1-12/+2
2015-05-08drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHVVille Syrjälä1-5/+31
2015-05-08drm/i915/skl: Make the Misc I/O power well part of the PLLS domainDamien Lespiau1-0/+1
2015-05-08drm/i915/skl: Add the INIT power domain to the MISC I/O power wellDamien Lespiau1-1/+2
2015-05-08drm/i915/skl: Assert the requirements to enter or exit DC6.Suketu Shah1-4/+36
2015-05-08Implement enable/disable for Display C6 stateA.Sunil Kamath1-2/+25
2015-05-08drm/i915/skl: Add DC6 Trigger sequence.Suketu Shah1-7/+36
2015-05-08drm/i915/skl: Assert the requirements to enter or exit DC5.Suketu Shah1-5/+46
2015-05-08drm/i915/skl: Implement enable/disable for Display C5 state.A.Sunil Kamath1-2/+39
2015-05-08drm/i915/skl: Add DC5 Trigger SequenceSuketu Shah1-0/+33
2015-04-16drm/i915/bxt: Implement enable/disable for Display C9 stateA.Sunil Kamath1-0/+66
2015-04-14drm/i915/bxt: Define BXT power domainsSatheeshakrishna M1-0/+55
2015-03-18drm/i915: Spelling s/auxilliary/auxiliary/Geert Uytterhoeven1-3/+3
2015-03-18drm/i915/skl: Restore the DDI translation tables when enabling PW1Damien Lespiau1-1/+3
2015-03-18drm/i915: Remove unused condition in hsw_power_well_post_enable()Damien Lespiau1-1/+1
2015-03-18drm/i915/skl: Restore pipe interrupt registers after power well enablingDamien Lespiau1-0/+31
2015-03-18drm/i915/skl: Mirror what we do on HSW for the power well enable log messageDamien Lespiau1-1/+1
2015-03-18drm/i915/skl: Introduce enable_requested and is_enabled in the power well codeDamien Lespiau1-4/+6
2015-03-18drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe maskDamien Lespiau1-1/+2
2015-02-14drm/i915/skl: Implementation of SKL display power well supportSatheeshakrishna M1-0/+220
2015-01-27drm/i915/skl: Adding power domains for AUX controllersSatheeshakrishna M1-0/+15
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-23 04:20:08 +0300