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path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
AgeCommit message (Expand)AuthorFilesLines
2014-08-20drm/i915/bdw: Make sure gpu reset still works with ExeclistsOscar Mateo1-0/+1
2014-08-13drm/i915: Fix up checks for aliasing ppgttDaniel Vetter1-3/+1
2014-08-12drm/i915/bdw: GEN-specific logical ring emit flushOscar Mateo1-7/+0
2014-08-12drm/i915/bdw: New logical ring submission mechanismOscar Mateo1-10/+12
2014-08-11drm/i915/bdw: GEN-specific logical ring initOscar Mateo1-13/+21
2014-08-11drm/i915/bdw: Generic logical ring init and cleanupOscar Mateo1-0/+17
2014-08-11drm/i915/bdw: Add a context and an engine pointers to the ringbufferDaniel Vetter1-0/+1
2014-08-11drm/i915/bdw: Allocate ringbuffers for Logical Ring ContextsOscar Mateo1-3/+3
2014-08-11drm/i915: Double check ring is idle before declaring the GPU wedgedChris Wilson1-1/+6
2014-08-08drm/i915: No busy-loop wait_for in the ring init codeDaniel Vetter1-2/+2
2014-08-08drm/i915: read HEAD register back in init_ring_common() to enforce orderingJiri Kosina1-0/+3
2014-08-07drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.Kenneth Graunke1-0/+9
2014-08-07drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.Kenneth Graunke1-15/+22
2014-07-23drm/i915: Use genX_ prefix for gt irq enable/disable functionsDaniel Vetter1-6/+6
2014-07-08drm/i915: HWS must be in the mappable region for g33Chris Wilson1-1/+15
2014-07-08drm/i915: Generalize ring_space to take a ringbufOscar Mateo1-7/+6
2014-07-08drm/i915: Extract ringbuffer destroy & generalize alloc to take a ringbufOscar Mateo1-10/+16
2014-07-08drm/i915/bdw: poll semaphoresBen Widawsky1-0/+1
2014-07-08drm/i915/bdw: implement semaphore waitBen Widawsky1-5/+30
2014-07-08drm/i915/bdw: implement semaphore signalBen Widawsky1-73/+112
2014-07-08drm/i915: Make semaphore updates more preciseBen Widawsky1-18/+9
2014-07-08drm/i915: gen specific ring initBen Widawsky1-76/+151
2014-07-07drm/i915: Fix VCS2's ring name.Rodrigo Vivi1-1/+1
2014-06-19drivers/i915: Fix unnoticed failure of init_ring_common()Konrad Zapalowicz1-0/+2
2014-06-17drm/i915: Added write-enable pte bit supporttAkash Goel1-0/+3
2014-06-13drm/i915/bdw: Do not write the Semaphore Sync Registers in GEN8+Oscar Mateo1-3/+4
2014-06-05drm/i915: Don't WARN about ring idle bit on gen2Ville Syrjälä1-1/+1
2014-05-23drm/i915: Split the ringbuffers from the rings (3/3)Oscar Mateo1-50/+59
2014-05-23drm/i915: Split the ringbuffers from the rings (2/3)Oscar Mateo1-51/+51
2014-05-23drm/i915: Split the ringbuffers from the rings (1/3)Oscar Mateo1-8/+45
2014-05-23drm/i915: s/intel_ring_buffer/intel_engine_csOscar Mateo1-78/+78
2014-05-20drm/i915/chv: Add some workaround notesVille Syrjälä1-1/+1
2014-05-16drm/i915: Bail out early on gen6_signal if no semaphoresMika Kuoppala1-0/+2
2014-05-13drm/i915: Ringbuffer signal func for the second BSD ringOscar Mateo1-0/+1
2014-05-12drm/i915: Use hash tables for the command parserBrad Volkin1-1/+5
2014-05-08drm/i915: Flush request queue when waiting for ring spaceChris Wilson1-25/+14
2014-05-08drm/i915: Improve fallback ring waitingChris Wilson1-6/+16
2014-05-05drm/i915: Support 64b execbufBen Widawsky1-8/+8
2014-05-05drm/i915: Move ring_begin to signal()Ben Widawsky1-17/+22
2014-05-05drm/i915: Virtualize the ringbuffer signal funcBen Widawsky1-17/+25
2014-05-05drm/i915: Move semaphore specific ring members to structBen Widawsky1-63/+61
2014-05-05drm/i915:Add the VCS2 switch in Intel_ring_setup_status_pageZhao Yakui1-0/+5
2014-05-05drm/i915:Initialize the second BSD ring on BDW GT3 machineZhao Yakui1-0/+78
2014-05-05drm/i915: Include a little more information about why ring init failsChris Wilson1-6/+5
2014-05-05drm/i915: Preserve ring buffers objects across resumeChris Wilson1-81/+87
2014-05-05drm/i915: Replace hardcoded cacheline size with macroChris Wilson1-13/+21
2014-04-09drm/i915: add flags to i915_ring_stopMika Kuoppala1-2/+6
2014-04-03drm/i915: Move all ring resets before setting the HWS pageChris Wilson1-20/+34
2014-04-03drm/i915: Invariably invalidate before ctx switchBen Widawsky1-7/+0
2014-04-02drm/i915: Enabling the TLB invalidate bit in GFX Mode registerAkash Goel1-1/+3
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