summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_dpll_mgr.c
AgeCommit message (Expand)AuthorFilesLines
2017-02-23Merge tag 'v4.10-rc8' into drm-nextDave Airlie1-1/+2
2017-02-08drm/i915/bxt: Add MST support when do DPLL calculationLee, Shawn C1-1/+2
2017-01-02drm/i915: Move intel_atomic_get_shared_dpll_state() to intel_dpll_mgr.cAnder Conselvan de Oliveira1-0/+31
2016-12-30drm/i915: Add dpll entrypoint for dumping hw stateAnder Conselvan de Oliveira1-0/+79
2016-12-30drm/i915: Update kerneldoc for intel_dpll_mgr.cAnder Conselvan de Oliveira1-5/+86
2016-12-30drm/i915: Rename intel_shared_dpll->mode_set() to prepare()Ander Conselvan de Oliveira1-4/+4
2016-12-30drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_stateAnder Conselvan de Oliveira1-36/+36
2016-12-30drm/i915: Rename intel_shared_dpll_commit() to _swap_state()Ander Conselvan de Oliveira1-1/+6
2016-12-30drm/i915: Introduce intel_release_shared_dpll()Ander Conselvan de Oliveira1-23/+18
2016-12-02drm/i915/glk: Update Port PLL enable sequence for GeminilkaeMadhav Chauhan1-0/+20
2016-12-02drm/i915/glk: Set DCC delay range 2 in PLL enable sequenceAnder Conselvan de Oliveira1-0/+6
2016-12-02drm/i915/glk: Implement Geminilake DDI init sequenceAnder Conselvan de Oliveira1-2/+2
2016-12-02drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira1-1/+1
2016-11-17drm/i915: Assorted INTEL_INFO(dev) cleanupsTvrtko Ursulin1-3/+2
2016-10-28drm/i915: Address broxton phy registers based on phy and channel numberAnder Conselvan de Oliveira1-38/+46
2016-10-14drm/i915: Make IS_BROXTON only take dev_privTvrtko Ursulin1-1/+1
2016-10-14drm/i915: Make IS_KABYLAKE only take dev_privTvrtko Ursulin1-1/+1
2016-10-14drm/i915: Make INTEL_PCH_TYPE & co only take dev_privTvrtko Ursulin1-1/+1
2016-10-14drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_privTvrtko Ursulin1-2/+2
2016-09-27drm/i915/bxt: Fix HDMI DPLL configurationImre Deak1-5/+16
2016-09-16drm/i915: do not use 'false' as a NULL pointerJani Nikula1-2/+2
2016-09-10drm/i915/dp: Add a standalone function to obtain shared dpll for HSW/BDW/SKL/BXTJim Bride1-0/+38
2016-09-07drm/i915: Split hsw_get_dpll()Manasi Navare1-33/+57
2016-09-07drm/i915: Split skl_get_dpll()Jim Bride1-48/+83
2016-09-07drm/i915: Split bxt_ddi_pll_select()Durgadoss R1-66/+102
2016-09-07drm/i915: Remove ddi_pll_sel from intel_crtc_stateAnder Conselvan de Oliveira1-27/+0
2016-08-23drm/i915: handle DP_MST correctly in bxt_get_dpllMaarten Lankhorst1-2/+8
2016-07-07drm/i915: s/INTEL_OUTPUT_DISPLAYPORT/INTEL_OUTPUT_DP/Ville Syrjälä1-3/+3
2016-07-05drm/i915: Convert dev_priv->dev backpointers to dev_priv->drmChris Wilson1-1/+1
2016-07-04drm/i915: Mass convert dev->dev_private to to_i915(dev)Chris Wilson1-6/+6
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson1-1/+5
2016-06-28drm/i915/bxt: Avoid early timeout during PLL enableImre Deak1-2/+2
2016-05-30drm/i915: Use crtc->name in debug messagesVille Syrjälä1-8/+8
2016-05-26drm/i915: Fix NULL pointer deference when out of PLLs in IVBAnder Conselvan de Oliveira1-0/+3
2016-05-23drm/i915: Unify SKL cdclk init pathsVille Syrjälä1-9/+2
2016-05-23drm/i915: Keep track of preferred cdclk vco frequency on SKLVille Syrjälä1-0/+5
2016-05-23drm/i915: Actually read out DPLL0 vco on skl from hardwareVille Syrjälä1-6/+0
2016-05-23drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()Ville Syrjälä1-4/+0
2016-05-23drm/i915/skl: SKL CDCLK change on modeset tracking VCOClint Taylor1-4/+5
2016-05-13drm/i915: Remove intel_clock_t typedefAnder Conselvan de Oliveira1-1/+1
2016-05-12drm/i915: s/DPPL/DPLL/ for SKL DPLLsVille Syrjälä1-3/+3
2016-04-15drm/i915/bxt: PORT_PLL_REF_SEL bit should be set for all BXT variationsDongwon Kim1-10/+2
2016-04-15drm/i915/bxt: Don't toggle power well 1 on-demandImre Deak1-4/+1
2016-04-15drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpersImre Deak1-2/+2
2016-04-11drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bitDongwon Kim1-1/+9
2016-04-07drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)Joonas Lahtinen1-1/+1
2016-03-31drm/i915: Add locking to pll updates, v3.Maarten Lankhorst1-6/+19
2016-03-17drm/i915: fix sparse warning for using false as NULLJani Nikula1-1/+1
2016-03-17drm/i915: Move pll power state to crtc power domains.Maarten Lankhorst1-4/+0
2016-03-17drm/i915: Perform dpll commit first, v2.Maarten Lankhorst1-1/+1
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-20 03:27:44 +0300